Multilevel template assisted wafer bonding

Patent metadata

Field	Value
Publication number	US-9922967-B2
Application number	US-201514862435-A
Country	US
Kind code	B2
Filing date	Sep 23, 2015
Priority date	Dec 8, 2010
Publication date	Mar 20, 2018
Grant date	Mar 20, 2018

Abstract

Fabricating a multilevel composite semiconductor structure includes providing a first substrate comprising a first material; dicing a second substrate to provide a plurality of dies; mounting the plurality of dies on a third substrate; joining the first substrate and the third substrate to form a composite structure; and joining a fourth substrate and the composite structure.

First claim

What is claimed is:

1. A method of fabricating a multilevel semiconductor structure, the method comprising:
providing a first substrate including a first plurality of devices;
providing a second substrate including a second plurality of devices;
dicing the second substrate to provide a plurality of dies, each die including one or more of the second plurality of devices;
providing a third substrate;
mounting the plurality of dies on predetermined portions of the third substrate;
aligning the first substrate and the third substrate;
joining the first substrate and the third substrate to form a composite structure;
removing at least a portion of the third substrate from the composite structure;
providing a fourth substrate;
aligning the fourth substrate with the composite structure after providing the fourth substrate; and
joining the fourth substrate and the composite structure, after aligning the fourth substrate with the composite structure, to form a semiconductor structure having multiple levels.

2. The method of fabricating the multilevel semiconductor structure as recited in claim 1 , wherein the first substrate is a silicon-on-insulator (SOI) substrate.

3. The method of fabricating the multilevel semiconductor structure as recited in claim 1 , wherein the first plurality of devices are silicon-based devices.

4. The method of fabricating the multilevel semiconductor structure as recited in claim 1 , wherein the first plurality of devices comprise photonic dies.

5. The method of fabricating the multilevel semiconductor structure as recited in claim 1 , wherein the second substrate is a compound semiconductor substrate.

6. The method of fabricating the multilevel semiconductor structure as recited in claim 1 , further comprising removing at least a portion of the fourth substrate from the semiconductor structure having multiple levels.

7. The method of fabricating the multilevel semiconductor structure as recited in claim 1 , wherein:
the plurality of dies is a first plurality of dies; and
the method further comprises mounting a second plurality of dies on predetermined portions of the fourth substrate before joining the fourth substrate and the composite structure.

8. The method of fabricating the multilevel semiconductor structure as recited in claim 1 , wherein the fourth substrate comprises silicon.

9. The method of fabricating the multilevel semiconductor structure as recited in claim 1 , further comprising forming an electrical interconnect in the composite structure.

10. The method of fabricating the multilevel semiconductor structure as recited in claim 1 , further comprising:
providing a fifth substrate;
aligning the fifth substrate with the semiconductor structure having multiple levels; and
joining the fifth substrate with the semiconductor structure having multiple levels.

11. The method of fabricating the multilevel semiconductor structure as recited in claim 10 , wherein the first substrate, the fourth substrate, and the fifth substrate comprise silicon.

12. The method of fabricating the multilevel semiconductor structure as recited in claim 1 , wherein the plurality of dies are seed dies and the method further comprises growing material on the seed dies.

13. The method of fabricating the multilevel semiconductor structure as recited in claim 1 , further comprising forming CMOS devices in the fourth substrate.

Assignees

• Skorpios Tech Inc

Inventors

• Krasulick Stephen B

Classifications

• G02B6/43

  Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections · CPC title

• G02B6/13

  Integrated optical circuits characterised by the manufacturing method · CPC title

• H01S5/021

  Silicon based substrates · CPC title

• G02B2006/12061

  Silicon · CPC title

• G02B6/00

  Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings · CPC title