Vertical integration of CMOS electronics with photonic devices

Patent metadata

Field	Value
Publication number	US-9659993-B2
Application number	US-201414482650-A
Country	US
Kind code	B2
Filing date	Sep 10, 2014
Priority date	Jan 18, 2012
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

A method of fabricating a composite semiconductor structure includes providing an SOI substrate including a plurality of silicon-based devices, providing a compound semiconductor substrate including a plurality of photonic devices, and dicing the compound semiconductor substrate to provide a plurality of photonic dies. Each die includes one or more of the plurality of photonics devices. The method also includes providing an assembly substrate having a base layer and a device layer including a plurality of CMOS devices, mounting the plurality of photonic dies on predetermined portions of the assembly substrate, and aligning the SOI substrate and the assembly substrate. The method further includes joining the SOI substrate and the assembly substrate to form a composite substrate structure and removing at least the base layer of the assembly substrate from the composite substrate structure.

First claim

What is claimed is:

1. A method of fabricating a composite semiconductor structure, the method comprising:
providing a substrate;
providing a photonic die, the photonic die comprising III-V material;
aligning the photonic die with the substrate;
joining the substrate and the photonic die to form a composite substrate; and
processing the composite substrate to form a feature on the photonic die, wherein:
the processing the composite substrate is performed after joining the substrate and the photonic die;
the feature on the photonic die is a stripe region; and
the stripe region is an optical waveguide.

2. The method of fabricating the composite semiconductor structure as recited in claim 1 , wherein the processing the composite substrate further includes forming an electrical interconnect on the photonic die.

3. The method of fabricating the composite semiconductor structure as recited in claim 1 , further comprising using an alignment tolerance of approximately ±10 μm for aligning the photonic die with the substrate.

4. The method of fabricating the composite semiconductor structure as recited in claim 1 , wherein the processing the composite substrate further forms an optical waveguide on the substrate.

5. The method of fabricating the composite semiconductor structure as recited in claim 1 , the method further comprising growing epitaxial layers on the photonic die after joining the substrate and the photonic die to form the composite substrate.

6. The method of fabricating the composite semiconductor structure as recited in claim 1 , the method further comprising:
providing an assembly substrate having a base layer and a device layer;
mounting the photonic die on a predetermined portion of the assembly substrate;
aligning the assembly substrate with the substrate to align the photonic die with the substrate; and
removing at least the base layer of the assembly substrate from the composite substrate after the photonic die and the substrate are joined.

7. The method of fabricating the composite semiconductor structure as recited in claim 1 , wherein:
the photonic die is a first photonic die; and
the method further comprises:
providing a second photonic die;
mounting the first photonic die and the second photonic die on an assembly substrate; and
aligning the assembly substrate with the substrate.

8. The method of fabricating the composite semiconductor structure as recited in claim 1 , wherein the substrate comprises a silicon-on-insulator (SOI) substrate.

9. The method of fabricating the composite semiconductor structure as recited in claim 1 , wherein the substrate comprises silicon-based devices.

Assignees

• Skorpios Tech Inc

Inventors

• Dallesasse John
• Krasulick Stephen B
• Creazzo Timothy
• Marchena Elton

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1916

  with separation or delamination along an ion implanted layer, e.g. Smart-cut · CPC title

• H01L27/14689 Primary

  Electricity · mapped topic

• H01L27/14643

  Electricity · mapped topic

• H01L27/0688

  Electricity · mapped topic