Interconnect structures with cobalt-infused ruthenium liner and a cobalt cap
US-2021242082-A1 · Aug 5, 2021 · US
Semiconductor device
US12444686B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12444686-B2 |
| Application number | US-202017928428-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 4, 2020 |
| Priority date | Jun 4, 2020 |
| Publication date | Oct 14, 2025 |
| Grant date | Oct 14, 2025 |
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- Title
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- Abstract
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Abstract
Official abstract text for this publication.
Provided is a semiconductor device, which has a wiring structure including a single-layer diffusion barrier layer having both a diffusion barrier function and a liner function. The semiconductor device has a wiring structure including an insulating layer, a conductive wiring, and a diffusion barrier layer disposed between the insulating layer and the conductive wiring in a manner of being in contact with both the insulating layer and the conductive wiring. The diffusion barrier layer is made of an alloy having an amorphous structure containing a first metal and a second element in an amount of 90% by mass or more in total. The first metal is any one selected from Co, Ru, and Mo. The second element is one or two or more selected from Zr, Al, and Nb when the first metal is Co, the second element is Zr when the first metal is Ru, and the second element is one or two selected from Y and B when the first metal is Mo.
First claim
Opening claim text (preview).
The invention claimed is: 1. A semiconductor device, which has a wiring structure including an insulating layer, a conductive wiring, and a diffusion barrier layer disposed between the insulating layer and the conductive wiring in a manner of being in contact with both the insulating layer and the conductive wiring, wherein the insulating layer contains a silicon oxide and/or a silicon oxide containing at least one element of C, N, and H, the conductive wiring contains Cu and/or Co, the diffusion barrier layer is made of an alloy having an amorphous structure containing a first metal and a second element in an amount of 90% by mass or more in total, the first metal is any one selected from Co, Ru, and Mo, wherein when the first metal is Co, the second element is one or two or more selected from Al, and Nb, wherein when the first metal is Ru, the second element is Zr, and wherein when the first metal is Mo, the second element is one or two selected from Y and B. 2. The semiconductor device according to claim 1 , wherein the diffusion barrier layer has a thickness of 5 nm or less. 3. The semiconductor device according to claim 1 , wherein the first metal is Co, and the second element is one or two or more selected from Al, and Nb. 4. The semiconductor device according to claim 1 , wherein the first metal is Ru and the second element is Zr. 5. The semiconductor device according to claim 1 , wherein the first metal is Mo, and the second element is one or two selected from Y and B. 6. The semiconductor device according to claim 2 , wherein the first metal is Co, and the second element is one or two or more selected from Al, and Nb. 7. The semiconductor device according to claim 2 , wherein the first metal is Ru and the second element is Zr. 8. The semiconductor device according to claim 2 , wherein the first metal is Mo, and the second element is one or two selected from Y and B.
Assignees
Inventors
Classifications
by forming openings in the dielectric parts · CPC title
by filling conductive material into holes, grooves or trenches · CPC title
- H10W20/033Primary
in openings in dielectrics · CPC title
the principal metal being a transition metal · CPC title
- H10W20/425Primary
Barrier, adhesion or liner layers · CPC title
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Frequently asked questions
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- What does patent US12444686B2 cover?
- Provided is a semiconductor device, which has a wiring structure including a single-layer diffusion barrier layer having both a diffusion barrier function and a liner function. The semiconductor device has a wiring structure including an insulating layer, a conductive wiring, and a diffusion barrier layer disposed between the insulating layer and the conductive wiring in a manner of being in co…
- Who is the assignee on this patent?
- Univ Tohoku
- What technology area does this patent fall under?
- Primary CPC classification H10W20/033. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Oct 14 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).