Semiconductor structure and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-2020118924-A1
Application number	US-201916714431-A
Country	US
Kind code	A1
Filing date	Dec 13, 2019
Priority date	Sep 26, 2017
Publication date	Apr 16, 2020
Grant date	—

Abstract

A method for manufacturing a semiconductor structure includes: forming a dielectric layer over a conductive layer on a semiconductor substrate; etching the dielectric layer to form a via hole that exposes the conductive layer; depositing a barrier layer to line the via hole; after depositing the barrier layer, depositing a first metal layer to fill a remainder of the via hole; performing a chemical mechanical polishing (CMP) process on the first metal layer until the barrier layer is exposed; after performing the CMP process, depositing a second metal layer over the barrier layer and the first metal layer; and etching the second metal layer to form a metal line.

First claim

What is claimed is:

1 . A method for manufacturing a semiconductor structure, comprising:
forming a dielectric layer over a conductive layer on a semiconductor substrate; etching the dielectric layer to form a via hole that exposes the conductive layer; depositing a barrier layer to line the via hole; after depositing the barrier layer, depositing a first metal layer to fill a remainder of the via hole; performing a chemical mechanical polishing (CMP) process on the first metal layer until the barrier layer is exposed; after performing the CMP process, depositing a second metal layer over the barrier layer and the first metal layer; and etching the second metal layer to form a metal line.

2 . The method of claim 1 , wherein depositing the first metal layer is performed to cover a portion of the barrier layer that extends along a top surface of the dielectric layer.

3 . The method of claim 1 , wherein after the CMP process is complete, a top surface of a remainder of the first metal layer is lower than a top end of the barrier layer.

4 . The method of claim 1 , wherein etching the second metal layer is performed by using a photolithography process.

5 . The method of claim 1 , wherein etching the second metal layer is performed such that a remainder of the barrier layer on a top surface of the dielectric layer has an end surface coterminous with a sidewall of the metal line.

6 . The method of claim 1 , further comprising:
forming a graphene layer extending along a top surface of the via after performing the CMP process and prior to forming the second metal layer.

7 . The method of claim 6 , wherein forming the graphene layer is performed such that the graphene layer is enclosed by a portion of the barrier layer that extends along a top surface of the dielectric layer.

8 . The method of claim 6 , wherein forming the graphene layer is performed without forming on a top end surface of the barrier layer.

9 . The method of claim 6 , wherein forming the graphene layer is performed at a higher process temperature than the via.

10 . The method of claim 6 , wherein forming the graphene layer is performed at a higher process temperature than the dielectric layer.

11 . A method for manufacturing a semiconductor structure, comprising:
depositing a first dielectric layer over a semiconductor substrate; forming a metal via extending through the first dielectric layer; depositing a metal layer over the first dielectric layer and the metal via; patterning the metal layer to form a metal line; forming a graphene layer to wrap around the metal line; after forming the graphene layer, depositing a second dielectric layer over the metal line; and performing a chemical mechanical polishing (CMP) process on the second dielectric layer, wherein the CMP process stops at the graphene layer.

12 . The method of claim 11 , wherein the metal line comprises a material different than the metal via.

13 . The method of claim 11 wherein forming the graphene layer is performed at a higher process temperature than the metal layer.

14 . The method of claim 11 , wherein forming the graphene layer is performed at a higher process temperature than the second dielectric layer.

15 . The method of claim 11 , wherein forming the graphene layer is performed such that a bottom end of the graphene layer is in contact with the first dielectric layer.

16 . The method of claim 11 wherein the CMP process is performed such that a top surface of the second dielectric layer is substantially level with a top surface of the graphene layer.

17 . A semiconductor structure, comprising:
a semiconductor substrate; a dielectric layer over the semiconductor substrate; a via extending through the dielectric layer; a barrier layer having a lower lateral portion extending along a bottom surface of the via, an inclined portion along a sidewall of the via and inclined with respect to the bottom surface of the via, and an upper lateral portion extending from a top end of the inclined portion along a top surface of the dielectric layer; and a metal line over the via and in contact with the upper lateral portion of the barrier layer.

18 . The semiconductor structure of claim 17 , wherein the upper lateral portion of the barrier layer extending along the top surface of the dielectric layer does not overlap the via.

19 . The semiconductor structure of claim 17 , further comprising a graphene layer extending along a top surface of the via and in contact with the barrier layer.

20 . The semiconductor structure of claim 19 , wherein the graphene layer has a maximal width greater than a maximal width of the via.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yang Shin-Yi
• Lee Ming-Han
• Shue Shau-Lin

Classifications

• H01L23/53252

  Electricity · mapped topic

• H01L23/53276

  Electricity · mapped topic

• H01L23/5283

  Electricity · mapped topic

• H01L23/53238

  Electricity · mapped topic

• H01L23/53266

  Electricity · mapped topic