Nonvolatile memory device and operating method thereof

Patent metadata

Field	Value
Publication number	US-12444470-B2
Application number	US-202318532730-A
Country	US
Kind code	B2
Filing date	Dec 7, 2023
Priority date	Jan 3, 2023
Publication date	Oct 14, 2025
Grant date	Oct 14, 2025

Abstract

Provided is an operating method of a nonvolatile memory device. The operating method includes receiving a read command, increasing a voltage applied to a plurality of unselected ground selection lines from an off voltage to an on voltage during a word line setup period, applying a first voltage to a first selected ground selection line corresponding to a first process characteristic, until a first time in the word line setup period, applying a second voltage to the first selected ground selection line after the first time in the word line setup period, applying the first voltage to a second selected ground selection line corresponding to a second process characteristic, until a second time earlier than the first time in the word line setup period, and applying the second voltage to the second selected ground selection line after the second time in the word line setup period.

First claim

What is claimed is:

1. An operating method of a nonvolatile memory device comprising a plurality of cell strings connected to a plurality of word lines, a plurality of string selection lines, and a plurality of ground selection lines, the operating method comprising:
receiving a read command;
in response to the read command, increasing a voltage of a plurality of unselected ground selection lines among the plurality of ground selection lines from an off voltage to an on voltage during a word line setup period;
applying a first voltage to a first selected ground selection line corresponding to a first process characteristic among a plurality of selected ground selection lines until a first time in the word line setup period;
applying a second voltage lower than the first voltage to the first selected ground selection line after the first time in the word line setup period;
applying the first voltage to a second selected ground selection line corresponding to a second process characteristic among the plurality of selected ground selection lines, until a second time earlier than the first time in the word line setup period; and
applying the second voltage to the second selected ground selection line after the second time in the word line setup period.

2. The operating method of claim 1 , further comprising:
applying the first voltage to a third selected ground selection line among the plurality of selected ground selection lines until a third time later than the first time in the word line setup period; and
applying the second voltage to the third selected ground selection line after the third time in the word line setup period,
wherein
each of the first selected ground selection line and the second selected ground selection line is adjacent to one of the plurality of unselected ground selection lines, and
the third selected ground selection line is not adjacent to the plurality of unselected ground selection lines.

3. The operating method of claim 2 , wherein each of the plurality of selected ground selection lines and the plurality of unselected ground selection lines is connected to transistors having a first threshold voltage lower than the second voltage or a second threshold voltage higher than the second voltage.

4. The operating method of claim 3 , wherein
the applying of the second voltage to the first selected ground selection line comprises applying the second voltage to a first transistor which is included in a first unselected cell string among the plurality of cell strings, is connected to the first selected ground selection line, and has the second threshold voltage, to turn off the first transistor, and
the applying of the second voltage to the second selected ground selection line comprises applying the second voltage to a second transistor which is included in a second unselected cell string among the plurality of cell strings, is connected to the second selected ground selection line, and has the second threshold voltage, to turn off the second transistor.

5. The operating method of claim 4 , wherein a time at which the first transistor is turned off is the same as a time at which the second transistor is turned off.

6. The operating method of claim 1 , wherein each of the first process characteristic and the second process characteristic includes at least one of a diameter of a channel connected to the plurality of ground selection lines, a word line thickness, an inter-wordline distance, or a wordline-to-channel distance.

7. The operating method of claim 6 , wherein the first process characteristic corresponds to a diameter of a first channel, and the second process characteristic corresponds to a diameter of a second channel smaller than the diameter of the first channel.

8. The operating method of claim 1 , further comprising:
applying a third voltage to first string selection lines corresponding to the plurality of selected ground selection lines among the plurality of string selection lines, until a fourth time earlier than the second time in the word line setup period;
applying a first negative voltage to a first unselected string selection line corresponding to the first process characteristic among the first string selection lines, after the fourth time in the word line setup period;
applying the third voltage to second string selection lines corresponding to the plurality of unselected ground selection lines among the plurality of string selection lines, until a fifth time earlier than the fourth time in the word line setup period; and
applying the first negative voltage to a second unselected string selection line corresponding to the first process characteristic among the second string selection lines, after the fifth time in the word line setup period.

9. The operating method of claim 8 , further comprising:
applying a fourth voltage higher than the first negative voltage to a third unselected string selection line corresponding to the second process characteristic among the first string selection lines, after the fourth time in the word line setup period; and
applying the fourth voltage to a fourth unselected string selection line corresponding to the second process characteristic among the second string selection lines, after the fifth time in the word line setup period.

10. The operating method of claim 8 , wherein each of the plurality of string selection lines comprises polysilicon.

11. An operating method of a nonvolatile memory device comprising a plurality of cell strings connected between a plurality of bit lines and a plurality of common source lines, the operating method comprising:
receiving a read command;
in response to the read command, increasing a voltage of a plurality of unselected ground selection lines from an off voltage to an on voltage during a word line setup period;
increasing a voltage of a plurality of selected ground selection lines to a pre pulse voltage by applying a first voltage to the plurality of selected ground selection lines until a first time in the word line setup period; and
decreasing the voltage of the plurality of selected ground selection lines to the off voltage by equally controlling a voltage gradient after the first time.

12. The operating method of claim 11 , wherein each of the plurality of selected ground selection lines and the plurality of unselected ground selection lines is connected to transistors having a first threshold voltage or a second threshold voltage higher than the first threshold voltage.

13. The operating method of claim 12 , wherein the decreasing of the voltage of the plurality of selected ground selection lines to the off voltage comprises turning off a first transistor which is included in an unselected cell string among the plurality of cell strings and has the second threshold voltage, by equally controlling a voltage gradient of the plurality of selected ground selection lines.

14. A nonvolatile memory device comprising:
a memory cell array comprising a plurality of cell strings connected to a plurality of word lines, a plurality of string selection lines, and a plurality of ground selection lines; and
a control circuit configured to control the memory cell array such that
a voltage of a plurality of unselected ground selection lines among the plurality of ground selection lines increases from an off voltage to an on voltage during a word line setup period,

in response to a read command, a first voltage is applied to a first selected ground selection line corresponding to a first process characteristic among a plurality of selected ground selection lines until a first time in the word line setup pe

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yu Jaeduk
• Park Jonghoon
• Lee Yohan
• Park Sangsoo

Classifications

• G11C16/08 Primary

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/0433 Primary

  comprising cells containing a single floating gate transistor and one or more separate select transistors · CPC title

• G11C16/32

  Timing circuits · CPC title

• G11C8/14

  Word line organisation; Word line lay-out · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title