Operation method operating nonvolatile memory device having plurality of memory blocks

Patent metadata

Field	Value
Publication number	US-9805807-B2
Application number	US-201615003113-A
Country	US
Kind code	B2
Filing date	Jan 21, 2016
Priority date	Mar 2, 2015
Publication date	Oct 31, 2017
Grant date	Oct 31, 2017

Abstract

A method of operating a nonvolatile memory device is provided as follows. The nonvolatile memory device includes memory blocks each of which has word lines. A setup voltage is applied to the word lines. A word line voltage is applied to a first word line selected from the word lines. Recovery voltages are applied to the word lines. Each recovery voltage is applied to at least one corresponding word line of the word lines. The recovery voltages have different voltage levels from each other.

First claim

What is claimed is:

1. A method of operating a nonvolatile memory device including a plurality of memory blocks, each memory block having a plurality of word lines, the method comprising:
applying a setup voltage to the word lines, wherein the word lines are divided into a plurality of recovery regions;
applying a word line voltage to a first word line selected from the word lines;
and
applying a plurality of recovery voltages to the plurality of recovery regions,
wherein each recovery voltage is applied to at least one corresponding word line of the word lines,
wherein the recovery voltages have different voltage levels from each other, and
wherein the voltage levels of the recovery voltages are different from a voltage level of the setup voltage.

2. The method of claim 1 ,
wherein the setup voltage is a pass voltage in a program operation.

3. The method of claim 2 ,
wherein the word line voltage is a program voltage in the program operation.

4. The method of claim 1 ,
wherein in a read operation, the setup voltage includes a word line setup voltage and a read pass voltage, the word line setup voltage being applied to the first word line and the read pass voltage being applied to the other of the word lines, and
wherein the read pass voltage is higher than the word line setup voltage.

5. The method of claim 4 ,
wherein the word line voltage comprises a read voltage.

6. The method of claim 5 ,
wherein the read voltage includes a first read voltage and a second read voltage higher than the first read voltage, and
wherein the applying of the word line voltage includes:
applying the first read voltage as the word line voltage to the first word line; and
after the applying of the first read voltage, applying the second read voltage as the word line voltage to the first word line.

7. The method of claim 1 ,
wherein the voltage levels of the recovery voltages are varied according to a temperature or a program/erase cycle.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Cheon An
• Park Mu-Hui
• Cho Jiho
• Lee Ji-Young
• Choi Yoon-Hee

Classifications

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/16 Primary

  for erasing blocks, e.g. arrays, words, groups · CPC title

• G11C16/3427

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title