Nonvolatile memory device and method of programming in the same

Patent metadata

Field	Value
Publication number	US-10629267-B2
Application number	US-201816213420-A
Country	US
Kind code	B2
Filing date	Dec 7, 2018
Priority date	Apr 16, 2018
Publication date	Apr 21, 2020
Grant date	Apr 21, 2020

Abstract

In a method of programming in a nonvolatile memory device, channels of a plurality of cell strings are precharged through ground selection transistors by a precharge voltage of a source line. A turn-on voltage is applied to a selected ground selection transistor of a selected cell string among the plurality of cell strings, during a verification read period of an N-th program loop. The turn-on voltage applied to the selected ground selection transistor is maintained to precharge the channels for an (N+1)-th program loop, without recovery after the verification read period of the N-th program loop is finished. Power consumption is reduced and an operation speed is increased by maintaining the turn-on voltage of the selected ground selection line to precharge the channels of the cell strings without recovery after the verification read operation is finished.

First claim

What is claimed is:

1. A method of programming a nonvolatile memory device comprising a plurality of cell strings, wherein a first cell string of the plurality of cell strings comprises a first string selection transistor, a first plurality of memory cells and a first ground selection transistor connected between a bit line and a source line, and wherein a second cell string of the plurality of cell strings comprises a second string selection transistor, a second plurality of memory cells and a second ground selection transistor connected between the bit line and the source line, the method comprising:
precharging a first channel of the first cell string through the first ground selection transistor by a precharge voltage of the source line and precharging a second channel of the second cell string through the second ground selection transistor by the precharge voltage of the source line;
applying a turn-on voltage to a selected ground selection transistor comprising the first ground selection transistor of a selected cell string comprising the first cell string, during a verification read period of an N-th program loop, wherein N is a natural number; and
maintaining the turn-on voltage applied to the selected ground selection transistor to further precharge the first channel of the first cell string for an (N+1)-th program loop, without recovery after the verification read period of the N-th program loop is finished.

2. The method of claim 1 , further comprising:
applying a turn-off voltage to an unselected ground selection transistor comprising the second ground selection transistor of an unselected cell string comprising the second cell string during the verification read period of the N-th program loop; and
applying the turn-on voltage to the unselected ground selection transistor to further precharge a second channel of the second cell string for the (N+1)-th program loop after a time point when the verification read period of the N-th program loop is finished.

3. The method of claim 2 , wherein the second channel is further precharged during a read recovery period of the N-th program loop and a bit line setup period of the (N+1)-th program loop.

4. The method of claim 1 , further comprising:
applying a verification read voltage to a selected word line among a plurality of word lines during the verification read period of the N-th program loop;
applying a read pass voltage to an unselected word line among the plurality of word lines during the verification read period of the N-th program loop; and
maintaining the read pass voltage applied to the unselected word line when the unselected word line is below the selected word line to further precharge channels comprising the first channel and the second channel for the (N+1)-th program loop, without recovery after the verification read period of the N-th program loop is finished.

5. The method of claim 4 , further comprising:
changing a time point of recovering the read pass voltage applied to the unselected word line that is below the selected word line, based on a location of the selected word line.

6. The method of claim 5 , wherein the time point of recovering the read pass voltage is further advanced in time as the selected word line is located at a lower position on the first cell string.

7. The method of claim 4 , further comprising:
maintaining the verification read voltage applied to the selected word line to further precharge the first channel of the first cell string for the (N+1)-th program loop, without recovery after the verification read period of the N-th program loop is finished; and
maintaining the read pass voltage applied to the unselected word line when the unselected word line is above the selected word line to further precharge the second channel of the second cell string for the (N+1)-th program loop, without recovery after the verification read period of the N-th program loop is finished.

8. The method of claim 1 , further comprising:
applying a first string turn-on voltage to a selected string selection transistor comprising the first string selection transistor of the selected cell string, during the verification read period of the N-th program loop; and
based on a location of a selected word line among a plurality of word lines, refraining from recovery of the first string turn-on voltage applied to an unselected string selection transistor comprising the second string selection transistor to further precharge a second channel of the second cell string for the (N+1)-th program loop after the verification read period of the N-th program loop is finished.

9. The method of claim 8 , wherein the refraining from recovery of the first string turn-on voltage is responsive to the selected word line being located below a reference word line.

10. The method of claim 8 , further comprising:
applying a second string turn-on voltage lower than the first string turn-on voltage to the selected string selection transistor after a time point when the verification read period of the N-th program loop is finished.

11. The method of claim 1 , further comprising:
changing the turn-on voltage applied to the selected ground selection transistor to further precharge the first channel of the first cell string, based on a location of a selected word line among a plurality of word lines.

12. The method of claim 11 , wherein the turn-on voltage applied to the selected ground selection transistor to further precharge the first channel of the first cell string is further decreased when the selected word line is located at a lower position on the first cell string than an unselected word line.

13. The method of claim 1 , further comprising:
changing the precharge voltage of the source line based on a number of performed program loops.

14. The method of claim 13 , wherein changing the precharge voltage of the source line based on the number of performed program loops comprises:
increasing the precharge voltage of the source line as the number of the performed program loops is increased.

15. The method of claim 1 ,
wherein the first cell string of the plurality of cell strings comprises a channel hole having a decreasing size toward a bottom end of the channel hole, and
wherein ones of the first plurality of the memory cells are programmed earlier as the ones of the first plurality of the memory cells are located at an upper position on the first cell string.

16. A method of programming a nonvolatile memory device comprising a plurality of cell strings, wherein a first cell string of the plurality of cell strings comprises a first string selection transistor, a first plurality of memory cells and a first ground selection transistor connected between a bit line and a source line, and wherein a second cell string of the plurality of cell strings comprises a second string selection transistor, a second plurality of memory cells and a second ground selection transistor connected between the bit line and the source line, the method comprising:
applying a turn-on voltage to a selected ground selection transistor comprising the first ground selection transistor of a selected cell string comprising the first cell string, during a verification read period of an N-th program loop, wherein N is a natural number;
maintaining the turn-on voltage applied to the selected ground selection transistor, without recovery after the verification read period of the N-th program loop is finished;
applying the turn-on voltage to an unselected ground selection transistor comprising the second ground selection transistor of an unselected cell string comp

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Kang-Bin
• Park Il-Han
• Jo Jong-Hoo

Classifications

• G11C16/3427

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C2211/5621

  Multilevel programming verification · CPC title

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title