Memory device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-12444466-B2
Application number	US-202017791326-A
Country	US
Kind code	B2
Filing date	Dec 28, 2020
Priority date	Jan 16, 2020
Publication date	Oct 14, 2025
Grant date	Oct 14, 2025

Abstract

A highly reliable memory device is provided. The memory device includes a first conductor, a second conductor above the first conductor, a third conductor above the second conductor, a fourth conductor above the third conductor, a fifth conductor above the fourth conductor, a sixth conductor above the fifth conductor, a seventh conductor, a first insulator, a second insulator, a first semiconductor, and a second semiconductor. At least third conductor and the fourth conductor have an opening. The first insulator, the first semiconductor, the second insulator, and the second semiconductor are provided in this order on an inner surface of the opening. The seventh conductor is provided between the first semiconductor and the second insulator in a region between the third conductor and the second insulator. The first semiconductor is electrically connected to the second conductor and the fifth conductor. The second semiconductor is electrically connected to the first conductor and the sixth conductor.

First claim

The invention claimed is:

1. A memory device comprising:
a first conductor;
a second conductor above the first conductor;
a third conductor above the second conductor;
a fourth conductor above the third conductor;
a fifth conductor above the fourth conductor;
a sixth conductor above the fifth conductor;
a seventh conductor;
a first insulator;
a second insulator;
a first semiconductor; and
a second semiconductor,
wherein an opening is provided through at least the second conductor, the third conductor, the fourth conductor, the fifth conductor, and the sixth conductor and reaches a top surface of the first conductor,
wherein the first insulator, the first semiconductor, the seventh conductor, the second insulator, and the second semiconductor are provided in this order from an outside in a first region of the opening that overlaps with the third conductor,
wherein the first insulator, the first semiconductor, the second insulator, and the second semiconductor are provided in this order from the outside in a second region of the opening that overlaps with the fourth conductor,
wherein the first semiconductor comprises a first portion in direct contact with a top surface of the second conductor and a second portion in direct contact with a side surface of the fifth conductor, and
wherein the second semiconductor comprises a first portion in direct contact with the top surface of the first conductor and a second portion in direct contact with a side surface of the sixth conductor.

2. The memory device according to claim 1 , wherein the first insulator, the first semiconductor, the seventh conductor, the second insulator, and the second semiconductor are each provided as a concentric layer in the first region of the opening.

3. The memory device according to claim 1 , wherein the first insulator, the first semiconductor, the second insulator, and the second semiconductor are each provided as a concentric layer in the second region of the opening.

4. The memory device according to claim 1 , wherein the first semiconductor is a first oxide semiconductor.

5. The memory device according to claim 4 ,
wherein the first oxide semiconductor comprises indium, an element M, and zinc, and
wherein the element M is one or more selected from aluminum, gallium, yttrium, tin, and titanium.

6. The memory device according to claim 1 , wherein the second semiconductor is a second oxide semiconductor.

7. The memory device according to claim 6 ,
wherein the second oxide semiconductor comprises indium, an element M, and zinc, and
wherein the element M is one or more selected from aluminum, gallium, yttrium, tin, and titanium.

8. The memory device according to claim 1 , wherein in a cross-sectional view, the second insulator comprises a portion in direct contact with a side surface of the second conductor.

9. The memory device according to claim 1 , wherein the first conductor is provided on a base.

10. A memory device comprising:
a first conductor;
a second conductor above the first conductor;
a third conductor above the second conductor;
a fourth conductor above the third conductor;
a fifth conductor above the fourth conductor;
a sixth conductor above the fifth conductor;
a seventh conductor;
a first insulator;
a second insulator;
a first semiconductor; and
a second semiconductor,
wherein an opening is provided through at least the second conductor, the third conductor, the fourth conductor, the fifth conductor, and the sixth conductor and reaches a top surface of the first conductor,
wherein the first insulator, the first semiconductor, the seventh conductor, the second insulator, and the second semiconductor are provided in this order from an outside in a first region of the opening that overlaps with the third conductor,
wherein the first insulator, the first semiconductor, the second insulator, and the second semiconductor are provided in this order from the outside in a second region of the opening that overlaps with the fourth conductor,
wherein the first semiconductor comprises a first portion in direct contact with a top surface of the second conductor and a second portion in direct contact with a side surface of the fifth conductor,
wherein the second semiconductor comprises a first portion in direct contact with the top surface of the first conductor and a second portion in direct contact with a side surface of the sixth conductor,
wherein the first conductor is configured to be a reading source line,
wherein the second conductor is configured to be a writing source line,
wherein the fifth conductor is configured to be a writing bit line, and
wherein the sixth conductor is configured to be a reading bit line.

11. The memory device according to claim 10 , wherein the first insulator, the first semiconductor, the seventh conductor, the second insulator, and the second semiconductor are each provided as a concentric layer in the first region of the opening.

12. The memory device according to claim 10 , wherein the first insulator, the first semiconductor, the second insulator, and the second semiconductor are each provided as a concentric layer in the second region of the opening.

13. The memory device according to claim 10 , wherein the first semiconductor is a first oxide semiconductor.

14. The memory device according to claim 13 ,
wherein the first oxide semiconductor comprises indium, an element M, and zinc, and
wherein the element M is one or more selected from aluminum, gallium, yttrium, tin, and titanium.

15. The memory device according to claim 10 , wherein the second semiconductor is a second oxide semiconductor.

16. The memory device according to claim 15 ,
wherein the second oxide semiconductor comprises indium, an element M, and zinc, and
wherein the element M is one or more selected from aluminum, gallium, yttrium, tin, and titanium.

17. The memory device according to claim 10 , wherein in a cross-sectional view, the second insulator comprises a portion in direct contact with a side surface of the second conductor.

18. The memory device according to claim 10 , wherein the first conductor is provided on a base.

Assignees

• Semiconductor Energy Lab

Inventors

• Tsuda Kazuki
• Godo Hiromichi
• Ohshita Satoru
• Kunitake Hitoshi
• Okamoto Satoru

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W72/50

  Bond wires · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10B41/30

  characterised by the memory core region · CPC title