Nonvolatile semiconductor memory device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9502431-B2
Application number	US-201514747167-A
Country	US
Kind code	B2
Filing date	Jun 23, 2015
Priority date	Sep 17, 2014
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

According to one embodiment, a memory device includes a first stacked layer structure stacked in order of a first insulating layer, a first electrode layer, . . . an n-th insulating layer, an n-th electrode layer, and an (n+1)-th insulating layer in a first direction perpendicular to a surface of a semiconductor substrate, where n is a natural number, an oxide semiconductor layer extending through the first to n-th electrode layers in the first direction, a second stacked layer structure provided between the first to n-th electrode layers and the oxide semiconductor layer, and including a charge storage layer which storages charges, and a area provided in the oxide semiconductor layer.

First claim

What is claimed is:

1. A nonvolatile semiconductor memory device comprising: a first stacked layer structure stacked in order of a first insulating layer, a first electrode layer, an n-th insulating layer, an n-th electrode layer, and an (n+1)-th insulating layer in a first direction, where n is a natural number; an oxide semiconductor layer extending through the first to n-th electrode layers in the first direction; a second stacked layer structure provided between the first to n-th electrode layers and the oxide semiconductor layer, and including a charge storage layer which storages charges; and an area provided in the oxide semiconductor layer, being in contact with at least one of the first to (n+1)-th insulating layers, having a composition ratio of oxygen lower than a composition ratio of oxygen in the oxide semiconductor layer.

2. The device of claim 1 ,
wherein at least one of the first to (n+1)-th insulating layers contacting the area comprises a material having a function which deoxidizes the oxide semiconductor layer.

3. The device of claim 1 ,
wherein at least one of the first to (n+1)-th insulating layers contacting the area comprises one layer selected from a group of a silicon oxide layer with silicon-rich and an insulating layer with hydrogen-rich.

4. The device of claim 1 ,
wherein at least one of the first to (n+1)-th insulating layers contacting the area comprises one layer selected from a group of a silicon oxide layer with silicon-rich and an insulating layer with hydrogen-rich, and further comprises two insulating layers sandwiching the one layer in the first direction.

5. The device of claim 1 ,
wherein the oxide semiconductor layer includes an element selected from a group of In, Ga, Zn, and Sn.

6. The device of claim 5 ,
wherein the oxide semiconductor layer is InGaZn-oxide.

7. The device of claim 1 ,
wherein the n is a natural number equal to or larger than 3,
each of the first and n-th electrode layers is a gate of a select transistor, and
each of the second to (n−1)-th electrode layers is a gate of a memory cell.

8. The device of claim 7 ,
wherein the n is a natural number equal to or larger than 4, and
the area is in contact with the third to (n−1)-th insulating layers.

9. The device of claim 7 ,
wherein the area is in contact with the second and n-th insulating layers.

10. The device of claim 7 ,
wherein the area is in contact with the first and (n+1)-th insulating layers.

11. The device of claim 1 ,
wherein the area surrounds the oxide semiconductor layer.

12. The device of claim 3 ,
wherein a width of the area in the first direction is substantially equal to a width of one layer selected from a group of the silicon oxide layer with silicon-rich and the insulating layer with hydrogen-rich contacting the area in the first direction.

13. The device of claim 1 ,
wherein the second stacked layer structure comprises a first insulating layer and a second insulating layer surrounding the oxide semiconductor layer, and
the charge storage layer is provided between the first insulating layer and the second insulating layer.

14. The device of claim 1 , further comprising:
a first conductive layer connected to a first end of the oxide semiconductor layer; and
a second conductive layer connected to a second end of the oxide semiconductor layer and extending in a second direction intersecting the first direction,
wherein the first to n-th electrode layers extend in a third direction intersecting the first and second directions.

15. The device of claim 14 ,
wherein the first conductive layer extends in the second or third directions.

16. The device of claim 1 ,
wherein the oxide semiconductor layer is provided around a core layer extending in the first direction.

17. The device of claim 1 ,
wherein the area has a resistance lower than a resistance of the oxide semiconductor layer.

18. A method of manufacturing the device of claim 1 , the method comprising:
forming a third stacked layer structure stacked in order of the first insulating layer, a first dummy layer, . . . the n-th insulating layer, an n-th dummy layer, and the (n+1)-th insulating layer in the first direction;
forming a dummy semiconductor layer extending through the first to n-th dummy layers in the first direction;
removing the first dummy layer to n-th dummy layer after forming the dummy semiconductor layer;
forming the second stacked layer structure and the first to n-th electrode layers surrounding the dummy semiconductor layer exposed by removing the first to n-th dummy layers; and
replacing the dummy semiconductor layer with the oxide semiconductor layer.

19. The method of claim 18 , further comprising:
forming the area contacting at least one of the first to (n+1)-th insulating layers in the oxide semiconductor layer by contacting the oxide semiconductor layer with the first to (n+1)-th insulating layers.

20. The method of claim 19 , further comprising:
forming the area by deoxidizing the oxide semiconductor layer and moving an oxygen in the oxide semiconductor layer to a silicon oxide layer with silicon-rich, when at least one of the first to (n+1)-th insulating layers contacting the area is the silicon oxide layer with silicon-rich.

21. The method of claim 19 , further comprising:
forming the area by deoxidizing the oxide semiconductor layer and moving a hydrogen in an insulating layer with hydrogen-rich to the oxide semiconductor layer, when at least one of the first to (n+1)-th insulating layers contacting the area is the insulating layer with hydrogen-rich.

Assignees

• Toshiba Kk

Inventors

• Sakuma Kiwamu
• Ota Kensuke
• Saitoh Masumi
• Tanaka Chika
• Matsushita Daisuke

Classifications

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10D62/80

  characterised by the materials · CPC title

• H10D30/693

  Vertical IGFETs having charge trapping gate insulators · CPC title

• H10D30/689 Primary

  Vertical floating-gate IGFETs · CPC title

• H01L29/66969

  Electricity · mapped topic