Memory device, electronic device, and operation method of memory device

Patent metadata

Field	Value
Publication number	US-12444460-B2
Application number	US-202318541218-A
Country	US
Kind code	B2
Filing date	Dec 15, 2023
Priority date	Dec 26, 2022
Publication date	Oct 14, 2025
Grant date	Oct 14, 2025

Abstract

Disclosed is a memory device which includes a pull-up driver that is connected between a power supply voltage and a first node, a T-coil circuit that is connected between the first node and a second node, an external resistor, and a ZQ controller that performs a ZQ calibration operation on the pull-up driver. The ZQ controller includes a path selecting circuit that selects one node among the first node and the second node, a comparing circuit that compares a voltage of the one node selected by the path selecting circuit with a pull-up reference voltage and outputs a comparison result, and a code generating circuit that generates a pull-up code for driving the pull-up driver, based on the comparison result. While the pull-up code is generated, the external resistor is connected between the second node and a ground voltage.

First claim

What is claimed is:

1. A memory device comprising:
a pull-up driver connected between a power supply voltage and a first node;
a T-coil circuit connected between the first node and a second node;
an external resistor; and
a ZQ controller configured to perform a ZQ calibration operation on the pull-up driver,
wherein the ZQ controller comprises:
a path selecting circuit configured to select one node among the first node and the second node;
a comparing circuit configured to:
compare a voltage of the one node selected by the path selecting circuit with a pull-up reference voltage, and
output a comparison result based the comparison between the voltage of the one node selected by the path selecting circuit and the pull-up reference voltage; and

a code generating circuit configured to generate a pull-up code for driving the pull-up driver, based on the comparison result, and
wherein, while the pull-up code is generated, the external resistor is connected between the second node and a ground voltage.

2. The memory device of claim 1 , wherein the path selecting circuit configured to select the one node among the first and second nodes based on designation of a ZQ calibration mode.

3. The memory device of claim 2 , wherein the ZQ calibration mode is designated, by an external memory controller, based on a reference resistance set to the pull-up driver corresponding to when the pull-up code is generated and a target resistance set to the pull-up driver corresponding to when the pull-up driver is driven.

4. The memory device of claim 1 , wherein, when the first node is selected by the path selecting circuit, the code generating circuit is configured to generate a first pull-up code, and
wherein, when the second node is selected by the path selecting circuit, the code generating circuit is configured to generate a second pull-up code.

5. The memory device of claim 4 , wherein the ZQ controller further comprises:
a ZQ register configured to store the first pull-up code and the second pull-up code.

6. The memory device of claim 5 , wherein the ZQ controller is configured to select one code among the first pull-up code and the second pull-up code, based on a target resistance of the pull-up driver, and
wherein the pull-up driver is configured to operate based on the selected one code among the first pull-up code and the second pull-up code.

7. The memory device of claim 4 , further comprising:
an offset compensator configured to:
generate an offset code corresponding to a resistance of the T-coil circuit, based on the first pull-up code and the second pull-up code; and
generate a compensated pull-up code based on the offset code.

8. The memory device of claim 7 , wherein the offset compensator is further configured to generate the compensated pull-up code by adjusting a compensation amount of the offset code based on a target resistance of the pull-up driver.

9. The memory device of claim 7 , wherein the pull-up driver comprises a plurality of pull-up circuits, and
wherein the offset compensator is further configured to generate the compensated pull-up code by adjusting a compensation amount of the offset code, based on the number of pull-up circuits activated during driving the pull-up driver from among the plurality of pull-up circuits.

10. The memory device of claim 7 , wherein the ZQ controller is further configured to:
provide the compensated pull-up code to the pull-up driver; and
generate a pull-down code for a pull-down driver connected between the pull-up driver and the ground voltage.

11. The memory device of claim 10 , wherein, in a data transmission operation of the memory device, the pull-up driver and the pull-down driver are connected in series between the power supply voltage and the ground voltage,
wherein the T-coil circuit is provided between the first node between the pull-up driver and the pull-down driver and an input/output pad, and
wherein, as the pull-up driver operates based on the compensated pull-up code and the pull-down driver operates based on the pull-down code, a data signal is output through the input/output pad.

12. The memory device of claim 10 , further comprising:
a plurality of second pull-up drivers; and
a plurality of second pull-down drivers,
wherein each of the plurality of second pull-up drivers operates based on the compensated pull-up code, and
wherein each of the plurality of second pull-down drivers operates based on the pull-up code.

13. The memory device of claim 1 , wherein the ZQ controller is configured to:
generate the pull-up reference voltage based on a reference resistance set to the pull-up driver corresponding to when the pull-up code is generated.

14. The memory device of claim 1 , further comprising:
a receiver configured to receive a data signal from an external memory controller through the T-coil circuit.

15. The memory device of claim 1 , further comprising:
a memory cell array comprising a plurality of dynamic random access memory (DRAM) cells;
a command and address buffer configured to receive and buffer command/address signals (CA) from an external memory controller;
an address decoder configured to receive an address signal from the command and address buffer and to decode the address signal;
a command decoder configured to receive a command signal from the command and address buffer and to decode the command signal;
a row decoder configured to control a plurality of word lines connected to the memory cell array depending on the address decoding result of the address decoder;
a columns decoder configured to control a plurality of bit lines connected to the memory cell array depending on the address decoding result of the address decoder;
an input/output circuit including the pull-up driver and the T-coil circuit, and configured to exchange data with the external memory controller; and
a control logic circuit configured to control the input/output circuit and the ZQ controller, based on the decoding result of the command decoder.

16. An operation method of a memory device, the method comprising:
generating a first pull-up code by comparing a first voltage at a first node between a pull-up driver and a T-coil circuit with a pull-up reference voltage;
generating a second pull-up code by comparing a second voltage at a second node between the T-coil circuit and an external resistor with the pull-up reference voltage;
generating an offset code corresponding to a resistance of the T-coil circuit, based on the first pull-up code and the second pull-up code; and
generating a compensated pull-up code, based on the offset code and a target resistance of the pull-up driver,
wherein the pull-up driver, the T-coil circuit, and the external resistor are connected in series between a power supply voltage and a ground voltage.

17. The method of claim 16 , further comprising:
driving the pull-up driver based on the compensated pull-up code; and
generating a pull-down code by comparing a third voltage of a third node between the pull-up driver and a pull-down driver and a pull-down reference voltage,
wherein the pull-up driver and the pull-down driver are connected in series between the power supply voltage and the ground voltage.

18. The method of claim 17 , further comprising:
outputting a data signal through the T-coil circuit by driving the pull-up driver based on the compensated pull-up code and driving the pull-down driver based on the pull-down code,
wherein the T-coil circuit is between the third node and a DQ pad.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jung Minsu
• Byun Jindo
• Kim Joohwan
• Shin Eun Seok
• Cho Hyun-Yoon
• Choi Junghwan

Classifications

• G11C11/4093

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title

• H03K19/01742

  by means of a pull-up or down element · CPC title

• G11C2207/2254

  Calibration · CPC title

• H03K19/01721

  by means of a pull-up or down element · CPC title

• G11C7/1057

  Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title