Storage devices and methods of operating the same

Patent metadata

Field	Value
Publication number	US-12443523-B2
Application number	US-202418744826-A
Country	US
Kind code	B2
Filing date	Jun 17, 2024
Priority date	Oct 11, 2023
Publication date	Oct 14, 2025
Grant date	Oct 14, 2025

Abstract

A method of operating a storage device including a nonvolatile memory device and a storage controller that is configured to control the nonvolatile memory device, the method comprising: partitioning the nonvolatile memory device into a plurality of domains; determining a scramble function based on a seed value of seed bits that correspond to a first portion of a plurality of address bits of a logical address among a plurality of logical addresses that are provided from a host device; generating a scrambled domain value based on the scramble function and a domain value of domain bits that correspond to a second portion of the plurality of address bits of the logical address among the plurality of logical addresses; and assigning a write operation that corresponds to the logical address to a domain that corresponds to the scrambled domain value among the plurality of domains.

First claim

What is claimed is:

1. A method of operating a storage device including a nonvolatile memory device and a storage controller that is configured to control the nonvolatile memory device, the method comprising:
partitioning the nonvolatile memory device into a plurality of domains;
determining a scramble function based on a seed value of seed bits that correspond to a first portion of a plurality of address bits of a logical address among a plurality of logical addresses that are provided from a host device;
generating a scrambled domain value based on the scramble function and a domain value of domain bits that correspond to a second portion of the plurality of address bits of the logical address among the plurality of logical addresses; and
assigning a write operation that corresponds to the logical address to a domain that corresponds to the scrambled domain value among the plurality of domains.

2. The method of claim 1 , further comprising:
setting a bit number of the domain bits based on a number of a plurality of channels that electrically connects the storage controller and the nonvolatile memory device.

3. The method of claim 1 , wherein the first portion corresponds higher bits of the plurality of address bits of the logical address among the plurality of logical addresses than the second portion.

4. The method of claim 3 , further comprising:
setting a third portion of the plurality of address bits of the logical address among the plurality of logical addresses to granularity bits that are lower bits of the plurality of address bits of the logical address among the plurality of logical addresses than the second portion.

5. The method of claim 4 , wherein, responsive to determining that a bit number of the granularity bits is a natural number M, write operations that correspond to 2 M of sequential logical addresses among the plurality of logical addresses are assigned to a same domain among the plurality of domains.

6. The method of claim 4 , further comprising:
setting a bit number of the granularity bits based on a memory capacity of the storage controller and a number of the plurality of domains.

7. The method of claim 1 , further comprising:
partitioning each domain of the plurality of domains into a plurality of sub domains.

8. The method of claim 7 , further comprising:
determining a sub scramble function based on a sub seed value of sub seed bits that correspond to a first portion of the seed bits;
generating a scrambled sub domain value based on the sub scramble function and a sub domain value of sub domain bits that correspond to a second portion of the seed bits; and
assigning the write operation that corresponds to the logical address among the plurality of logical addresses to a sub domain that corresponds to the scrambled sub domain value among the plurality of sub domains.

9. The method of claim 8 , further comprising:
setting a bit number of the domain bits based on a number of a plurality of channels that electrically connects the storage controller and the nonvolatile memory device; and
setting a bit number of the sub domain bits based on a number of ways that are electrically connected to each channel of the plurality of channels.

10. The method of claim 1 , further comprising: receiving a request from the host device for performing a same operation with respect to an address range that includes a plurality of sequential logical addresses among the plurality of logical addresses; and
classifying the address range into a body range and an edge range responsive to the receiving the request.

11. The method of claim 10 , wherein the body range includes unit ranges, and
wherein, responsive to determining that a bit number of the seed bits is N, where N is a natural number, each of the unit ranges includes 2 N of sequential logical addresses that correspond to a same seed value among the plurality of sequential logical addresses.

12. The method of claim 10 , wherein the generating the scrambled domain value comprises:
omitting the generating the scrambled domain value with respect to first logical addresses that correspond to the body range among the plurality of sequential logical addresses among the plurality of logical addresses, and
wherein the generating the scrambled domain value includes generating the scrambled domain value with respect to second logical addresses that correspond to the edge range among the plurality of sequential logical addresses among the plurality of logical addresses.

13. The method of claim 12 , further comprising:
performing the same operation with respect to the first logical addresses that correspond to the body range based on the domain value; and
performing the same operation with respect to the second logical addresses that correspond to the edge range based on the scrambled domain value.

14. A storage device comprising:
a nonvolatile memory device that includes a plurality of domains; and
a storage controller that is configured to control the nonvolatile memory device,
the storage controller including:
a scramble circuit that is configured to determine a scramble function based on a seed value of seed bits that correspond to a first portion of a plurality of address bits of a logical address among a plurality of logical addresses that are provided from a host device and is configured to generate a scrambled domain value based on the scramble function and a domain value of domain bits that correspond to a second portion of the plurality of address bits of the logical address among the plurality of logical addresses; and
a processor that is configured to assign a write operation that corresponds to the logical address to a domain that corresponds to the scrambled domain value among the plurality of domains.

15. The storage device of claim 14 , wherein, a bit number of granularity bits that correspond to a third portion of the plurality of address bits of the logical address among the plurality of logical addresses is a natural number M, and
wherein the processor is configured to assign write operations that correspond to 2 M of sequential logical addresses among the plurality of logical addresses to a same domain among the plurality of domains.

16. The storage device of claim 14 , wherein the scramble circuit is configured to partition each domain of the plurality of domains into a plurality of sub domains, determine a sub scramble function based on a sub seed value of sub seed bits that correspond to a first portion of the seed bits, and generate a scrambled sub domain value based on the sub scramble function and a sub domain value of sub domain bits that correspond to a second portion of the seed bits, and
wherein the processor is configured to assign the write operation that corresponds to the logical address among the plurality of logical addresses to a sub domain that corresponds to the scrambled sub domain value among the plurality of sub domains.

17. The storage device of claim 14 , wherein the storage controller further includes:
a range operation controller that is configured to, responsive to receiving a request from the host device for performing a same operation with respect to an address range including a plurality of sequential logical addresses among the plurality of logical addresses, classify the address range into a body range and an edge range excluding the body range.

18. The storage device of claim 17 , wherein the range operation controller is configured to provide logical addresses that correspond to the body range to the processor and

Assignees

• Samsung Electronics Co Ltd

Inventors

• Choi Hyunjin
• Noh Sunghyun
• Lee Hyuk
• Mun Kuiyon

Classifications

• G06F13/1668

  Details of memory controller · CPC title

• G06F13/4068 Primary

  Electrical coupling · CPC title

• G06F2212/1032

  Reliability improvement, data loss prevention, degraded operation etc · CPC title

• G06F2212/1016

  Performance improvement · CPC title

• G06F3/0658

  Controller construction arrangements · CPC title