XOR-based scrambler/descrambler for SSD communication protocols

Patent metadata

Field	Value
Publication number	US-10121013-B2
Application number	US-201615064191-A
Country	US
Kind code	B2
Filing date	Mar 8, 2016
Priority date	May 7, 2015
Publication date	Nov 6, 2018
Grant date	Nov 6, 2018

Abstract

Example embodiments for descrambling and scrambling a memory channel include executing a training mode for the memory device to discover XOR vectors used by the host system to scramble data. The training mode inputs all zero training data to a scrambling algorithm for all memory locations of the memory device to generate scrambled training data that is transmitted over the memory channel to the memory device. The scrambled training data are equal to the XOR vectors corresponding to those memory locations. The scrambled training data is received over the memory channel by the memory device and stored as the XOR vectors for each corresponding memory location. During a functional mode, the scrambled data is received over the memory channel for a specified memory location and the XOR vector stored for the specified memory location is used to descramble the scrambled data prior to writing to the specified memory location.

First claim

We claim:

1. A method for descrambling and scrambling data transmitted via a memory channel of a memory device coupled to a host system, the method, comprising:
executing a training mode for the memory device to discover XOR vectors used by the host system to scramble data by:
inputting all zero training data to a scrambling algorithm for all memory locations of the memory device to generate scrambled training data that is transmitted over the memory channel to the memory device, such that the scrambled training data are equal to the XOR vectors corresponding to those memory locations;

receiving the scrambled training data over the memory channel by the memory device and storing the scrambled training data as the XOR vectors for each of the corresponding memory locations; and
after the training mode and during a functional mode of the memory device, receiving, by the memory device, scrambled data over the memory channel for a specified memory location, and using an XOR vector of the XOR vectors stored for the specified memory location to descramble the scrambled data prior to writing to the specified memory location.

2. The method of claim 1 , further comprising:
when reading the data from the specified memory location during the functional mode, retrieving the data and using the XOR vector stored for the specified memory location to scramble the data prior to transmitting the scrambled data over the memory channel to the host system.

3. The method of claim 1 , wherein a storage device driver on the host system initiates the training mode.

4. The method of claim 1 , wherein during the training mode a storage controller on the memory device receives the scrambled training data and a descrambling and scrambling algorithm stores the XOR vectors.

5. The method of claim 4 , wherein the memory device includes a vector storage memory that stores the XOR vectors.

6. The method of claim 1 , wherein receiving the scrambled data during the functional mode further comprises:
retrieving, by a descrambling and scrambling algorithm on the memory device, the XOR vector for the specified memory location from a vector storage memory of the memory device and performing an exclusive-OR operation on the XOR vector and the scrambled data to generate descrambled data, which is then stored in the specified memory location.

7. The method of claim 1 , wherein the scrambled data received during the functional mode includes at least one of: Control/Descriptor data, Status data, User data, and Control data.

8. The method of claim 7 , wherein when the scrambled data includes the Control/Descriptor data, a descrambling and scrambling algorithm on the memory device stores the XOR vector for each corresponding control/descriptor memory location during the training mode.

9. The method of claim 8 , wherein when the descrambling and scrambling algorithm uses the XOR vectors to descramble the Control/Descriptor data during the functional mode.

10. The method of claim 7 , wherein when the scrambled data includes Status data, a descrambling and scrambling algorithm on the memory device stores the XOR vector for each corresponding status memory location during the training mode.

11. The method of claim 10 , wherein when the descrambling and scrambling algorithm uses the XOR vectors to scramble the Status data during the functional mode.

12. The method of claim 7 , wherein when the scrambled data includes the User data and Control data, a descrambling and scrambling algorithm on the memory device stores the XOR vector for each corresponding User data memory location during the training mode.

13. The method of claim 12 , wherein when the descrambling and scrambling algorithm uses the XOR vectors to scramble the User data and Control data during a read of the memory device during the functional mode; and for a write to the memory device during the functional mode, the descrambling algorithm descrambles the User data and the Control data prior to writing to the memory device.

14. The method of claim 7 , further comprising:
storing the XOR vectors in a vector storage memory on the memory device, wherein the vector storage memory is partitioned into different areas including one or more of: a Control/Descriptor data vector area, a Status data vector area, a User data vector area, and a Control data vector area, to store the XOR vectors for the corresponding type of data.

15. A system for descrambling and scrambling data transmitted via a memory channel of a memory device coupled to a host system, comprising:
a storage device driver installed on the host system that executes a training mode for the memory device to discover XOR vectors used by the host system to scramble data by:
inputting all zero training data to a scrambling algorithm for all memory locations of the memory device to generate scrambled training data that is transmitted over the memory channel to the memory device, such that the scrambled training data are equal to the XOR vectors corresponding to those memory locations; and

a storage controller on the memory device configured to:
receive the scrambled training data over the memory channel and store the scrambled training data as the XOR vectors for each of the corresponding memory locations; and
after the training mode and during a functional mode of the memory device, receive scrambled data over the memory channel for a specified memory location, and use an XOR vector of the XOR vectors stored for the specified memory location to descramble the scrambled data prior to writing to the specified memory location.

16. The system of claim 15 , wherein when reading the data from the specified memory location during the functional mode, the memory device retrieves the data and uses the XOR vector stored for the specified memory location to scramble the data prior to transmitting the scrambled data over the memory channel to the host system.

17. The system of claim 15 , wherein during the training mode a storage controller on the memory device receives the scrambled training data and a descrambling algorithm stores the XOR vectors.

18. The system of claim 17 , wherein the memory device includes a vector storage memory that stores the XOR vectors.

19. The system of claim 15 , wherein while receiving scrambled data during functional mode, a descrambling and scrambling algorithm on the memory device retrieves the XOR vector for the specified memory location from a vector storage memory of the memory device and performs an exclusive-OR operation on the XOR vector and the scrambled data to generate descrambled data, which is then stored in the specified memory location.

20. The system of claim 15 , wherein the scrambled data received during functional mode includes at least one of: Control/Descriptor data, Status data, User data, and Control data.

21. The system of claim 20 , wherein when the scrambled data includes the Control/Descriptor data, a descrambling and scrambling algorithm on the memory device stores the XOR vector for each corresponding control/descriptor memory location during the training mode.

22. The system of claim 21 , wherein the descrambling and scrambling algorithm uses the XOR vectors to descramble the Control/Descriptor data during the functional mode.

23. The system of claim 20 , wherein when the scrambled data includes Status data, a descrambling and scrambling algorithm on the memory device stores the XOR vector for each corresponding status memory location during t

Assignees

• Samsung Electronics Co Ltd

Inventors

• CHANG Chihjen
• Bekerman Michael
• Swarbrick Ian
• Hanson Craig

Classifications

• G06F21/79

  in semiconductor storage media, e.g. directly-addressable memories · CPC title

• H04L9/065

  Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3 · CPC title

• G06F21/606 Primary

  by securing the transmission between two devices or processes · CPC title

• G06F3/062 Primary

  Securing storage systems · CPC title

• G09C1/00

  Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system (cryptographic typewriters G09C3/00) · CPC title