I/O channel scrambling/ECC disassociated communication protocol

Patent metadata

Field	Value
Publication number	US-10025747-B2
Application number	US-201514967258-A
Country	US
Kind code	B2
Filing date	Dec 11, 2015
Priority date	May 7, 2015
Publication date	Jul 17, 2018
Grant date	Jul 17, 2018

Abstract

A protocol that enables communication between a host and an Input/Output (I/O) channel storage device, such as a Dynamic Random Access Memory (DRAM) channel Dual In-Line Memory Module (DIMM) form-factor Solid State Drive (SSD), without the need to know or reverse engineer the encoding applied by the host. The control/status data are written to the storage device by sending a protocol training sequence of known values and storing the associated command/status data in the storage device in the same encoding format as that received from the host. These stored values are used at run time to execute encoded commands received from the host and to report status data to the host in the host-recognizable manner. A memory bank-based buffered configuration stores user data also in the as-received condition to preserve the host-specific encoding. This facilitates exchange of user data between the host memory controller and the storage device over the DRAM channel.

First claim

What is claimed is:

1. A method comprising:
detecting that a storage device is attached to Input/Output (I/O) interface supported by a host;
in response to said detecting, instructing the host to write a first sequence of data patterns to the storage device using the I/O interface, wherein a data pattern in the first sequence includes an encoded version of respective command data bits of an I/O command, and wherein the data pattern in the first sequence is written a pre-determined number of times before a next data pattern in the first sequence is written to the storage device, wherein the pre-determined number is greater than one;
storing a command data-containing portion of the written data pattern in an addressable storage in the storage device;
receiving, at the storage device, a control bit pattern from the host over the I/O interface, wherein the control bit pattern includes an encoded I/O command; and
using one or more command data-containing portions in the addressable storage to decode the encoded I/O command received through the control bit pattern.

2. The method of claim 1 , wherein the I/O interface is a Dynamic Random Access Memory (DRAM) interface, the encoded I/O command is an encoded DRAM command, and the storage device is configured to operate via the DRAM interface.

3. The method of claim 1 , wherein instructing the host to write the first sequence of data patterns includes:
establishing a control register within the storage device, wherein the control register is configured to store at least the command data-containing portion of the data pattern in the first sequence;
associating a memory address with the control register; and
instructing the host to write the data pattern in the first sequence to the memory address associated with the control register.

4. The method of claim 1 , further comprising:
further instructing the host to write a second sequence of data patterns to the storage device using the I/O interface, wherein a data pattern in the second sequence includes an encoded version of a respective status data, and wherein the data pattern in the second sequence is written the pre-determined number of times before a next data pattern in the second sequence is written to the storage device;
storing a status data-containing portion of the data pattern in the second sequence in a register in the storage device;
decoding the received I/O command using the addressable storage;
accessing the register in the storage device;
based on a result of an operation, retrieving a corresponding status data-containing portion from the register; and
providing the retrieved status data-containing portion to the host as a response to the received I/O command.

5. The method of claim 4 , wherein the data pattern in the first sequence and the data pattern in the second sequence are written in a pre-defined order known to the storage device.

6. The method of claim 4 , wherein instructing the host to write the second sequence of data patterns includes:
establishing a status register within the storage device, wherein the status register is configured to store at least the status data-containing portion of the data pattern in the second sequence;
associating a memory address with the status register; and
instructing the host to write the data pattern in the second sequence to the memory address associated with the status register.

7. The method of claim 4 , wherein the data patterns in the first and the second sequences are sent to the storage device by the host in transmission formats defined for the I/O interface.

8. A method comprising:
configuring a storage device to be attachable to and operable through an Input/Output (I/O) interface supported by a host, wherein the storage device is configured to store data received from the host in a plurality of buffers within the storage device;
receiving, at the storage device, the following from the host via the I/O interface:
a memory-mapped buffer address of one of the plurality of buffers, and
an encoded version of a memory page of data;

storing the encoded version of the received memory page of data into the buffer having the memory-mapped buffer address;
receiving an instruction from the host to read a content stored at the memory-mapped buffer address; and
in response to receiving the instruction, providing the stored encoded version of the received memory page of data to the host via the I/O interface.

9. The method of claim 8 , wherein the configuring includes:
upon attachment to the I/O interface, training the storage device to recognize host-encoded memory commands so as to enable the storage device to execute the memory commands received from the host over the I/O interface regardless of a first encoding scheme used by the host to encode the memory commands; and
further training the storage device to provide an encoded version of a status information to the host, wherein the status information is sent over the I/O interface and is associated with execution of a corresponding memory command, and wherein the encoded version of the status information is based on a second encoding scheme used by the host to process the status information.

10. The method of claim 8 , wherein the I/O interface is a Dynamic Random Access Memory (DRAM) interface, and wherein configuring the storage device includes:
partitioning each buffer into a plurality of blocks, wherein each block is accessible using a corresponding Logical Block Address (LBA), and wherein a size of each block is equal to a size of the memory page of data received from the host; and
organizing the plurality of buffers into a plurality of memory banks, wherein each memory bank contains an identical number of different buffers and is separately addressable by the host as if the memory bank were a DRAM memory bank connected to the DRAM interface, and
wherein, receiving from the host a memory-mapped buffer address of a given buffer in the plurality of buffers includes:
receiving a memory-mapped buffer address that identifies a memory bank associated with the given buffer as well as the given buffer within the identified memory bank.

11. The method of claim 10 , further comprising:
assigning a respective plurality of LBAs to each block in the plurality of blocks using set-associativity.

12. A memory module, comprising:
a first storage portion that includes a plurality of memory units to store content;
an interface unit configured to allow the memory module to be attached to and operable through an Input/Output (I/O) interface supported by a host;
a second storage portion; and
a control unit coupled to the first storage portion, the interface unit, and the second storage portion, wherein, upon attachment of the memory module to the I/O interface, the control unit is operative to:
receive from the host a first sequence of data patterns over the I/O interface, wherein a data pattern in the first sequence includes an encoded version of respective command data bits of an I/O command, and wherein the data pattern in the first sequence is received from the host a pre-determined number of times before a next data pattern in the first sequence is received, wherein the pre-determined number is greater than one;
store a command data-containing portion of the written data pattern in the second storage portion;
receive a control bit pattern from the host over the I/O interface, wherein the control bit pattern includes an encoded I/O command; and
use one or more command data-containing portions in the second storage portion to decode the encoded I/O command received through the control bit pattern.

13. The memory modu

Assignees

• Swarbrick Ian
• Bekerman Michael
• Hanson Craig
• CHANG Chihjen
• Samsung Electronics Co Ltd

Inventors

• Swarbrick Ian
• Bekerman Michael
• Hanson Craig
• CHANG Chihjen

Classifications

• G06F13/1678 Primary

  using bus width · CPC title

• G06F13/4234 Primary

  being a memory bus · CPC title