Optically bridged multicomponent package with extended temperature range

Patent metadata

Field	Value
Publication number	US-12443000-B2
Application number	US-202519170617-A
Country	US
Kind code	B2
Filing date	Apr 4, 2025
Priority date	Mar 18, 2022
Publication date	Oct 14, 2025
Grant date	Oct 14, 2025

Abstract

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

First claim

What is claimed is:

1. A bridge comprising:
a plurality of interfaces comprising four interfaces, wherein:
each interface is an electrical interface configured to connect electrically a respective die to the bridge,
each interface includes a serializer and deserializer for any die connected to the bridge through the interface; and

a photonic network, wherein:
the photonic network includes a directional photonic link from the serializer of each of the four interfaces to the deserializer of each of the remaining three interfaces, whereby the photonic network and the interfaces provide six bidirectional photonic communication paths ending at the four interfaces and every interface of the four interfaces is bidirectionally coupled to every other of the four interfaces.

2. The bridge of claim 1 , wherein the four interfaces are arranged in two dimensions, and the six communication paths are two horizontal paths, two vertical paths, and two diagonal paths.

3. The bridge of claim 1 , wherein each of the four interfaces comprises a respective analog/mixed signal (AMS) block that comprises the serializer and deserializer of the interface.

4. The bridge of claim 1 , wherein the photonic links of the photonic network are implemented in a bridge substrate.

5. The bridge of claim 4 , wherein the bridge substrate is an integrated circuit.

6. The bridge of claim 5 , wherein each AMS block is disposed on the bridge substrate.

7. The bridge of claim 1 , further comprising an optical interface coupled to the photonic network.

8. The bridge of claim 1 , further comprising four dies each connected to the bridge through a respective interface, wherein the four dies include at least one die with a memory region.

9. The bridge of claim 8 , wherein the four dies each are rectangular and are laterally or diagonally adjacent to each other.

10. The bridge of claim 8 , wherein the four dies are each electrically coupled to the bridge.

11. The bridge of claim 3 , wherein the four dies are each electrically connected to respective AMS blocks through electrical paths in the bridge.

12. The bridge of claim 4 , wherein the four interfaces are arranged in two dimensions, and the six communication paths are two horizontal paths, two vertical paths, and two diagonal paths.

13. The bridge of claim 4 , wherein each of the four interface comprises a respective analog/mixed signal (AMS) block that comprises the serializer and deserializer of the interface.

14. The bridge of claim 4 , wherein the photonic links of the photonic network are implemented in a bridge substrate.

15. The bridge of claim 5 , wherein the four interfaces are arranged in two dimensions, and the six communication paths are two horizontal paths, two vertical paths, and two diagonal paths.

16. The bridge of claim 5 , wherein each of the four interfaces comprises a respective analog/mixed signal (AMS) block that comprises the serializer and deserializer of the interface.

17. The bridge of claim 5 , wherein the photonic links of the photonic network are implemented in a bridge substrate comprising an integrated circuit.

18. The bridge of claim 8 , wherein the four interfaces are arranged in two dimensions, and the six communication paths are two horizontal paths, two vertical paths, and two diagonal paths.

19. The bridge of claim 8 , wherein each of the four interface comprises a respective analog/mixed signal (AMS) block that comprises the serializer and deserializer of the interface.

20. The bridge of claim 8 , wherein the photonic links of the photonic network are implemented in a bridge substrate comprising an integrated circuit.

21. The bridge of claim 8 , further comprising an optical interface coupled to the photonic network.

Assignees

• Celestial Ai Inc

Inventors

• Winterbottom Philip
• Lazovsky David
• Aggarwal Ankur
• Bos Martinus
• Sahni Subal

Classifications

• H04B10/801

  using optical interconnects, e.g. light coupled isolators, circuit board interconnections · CPC title

• H04B10/40

  Transceivers · CPC title

• G02B6/4274

  Electrical aspects (G02B6/4263 and G02B6/4265 take precedence) · CPC title

• G02B6/428

  containing printed circuit boards [PCB] · CPC title

• G02F1/0123 Primary

  Circuits for the control or stabilisation of the bias voltage, e.g. automatic bias control [ABC] feedback loops · CPC title