Optically bridged multicomponent package with extended temperature range

Patent metadata

Field	Value
Publication number	US-12442997-B2
Application number	US-202519170416-A
Country	US
Kind code	B2
Filing date	Apr 4, 2025
Priority date	Mar 18, 2022
Publication date	Oct 14, 2025
Grant date	Oct 14, 2025

Abstract

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

First claim

What is claimed is:

1. A package, comprising:
a package substrate;
a bridging element disposed in the package substrate, the bridging element providing an optical bridge among a plurality of dies;
one or more analog/mixed signal (AMS) blocks coupled to the bridging element, the one or more AMS blocks configured for implementing data serialization and deserialization interfaces between the dies and the bridging element;
a photonic network, disposed in the bridging element, comprising a plurality of photonic paths;
a first photonic transceiver disposed in the bridging element, the first photonic transceiver optically coupled to the photonic network and electrically coupled, via a first set of one or more electrical interconnects, to the one or more AMS blocks;
a second photonic transceiver disposed in the bridging element, the second photonic transceiver optically coupled to the photonic network and electrically coupled, via a second set of one or more electrical interconnects, to the one or more AMS blocks;
an optical input disposed in the bridging element, the optical input providing an optical connection to light from an external device; and
a splitter disposed in the bridging element, the splitter coupled to the optical input via the photonic network and further coupled to the first and the second photonic transceivers via the photonic network, and wherein the splitter is configured for distributing the light over different photonic paths in the photonic network, wherein
the one or more AMS blocks are aligned with the bridging element such that each of the one or more electrical interconnects in the first and second sets of the electrical interconnects is less than 2 mm in length.

2. The package of claim 1 , wherein the one or more AMS blocks comprise a first serializer, a first deserializer, a second serializer, and a second deserializer, and wherein the first serializer and first deserializer are coupled to a first die through a first digital interface, and the second serializer and second deserializer are coupled to a second die through a second digital interface.

3. The package of claim 2 , wherein the first or second digital interface comprises one of UCIe (Universal Chiplet Interconnect Express) or PCIe (Peripheral Component Interconnect Express).

4. The package of claim 1 , wherein the optical input is coupled to the external device with one or more optical fibers.

5. The package of claim 4 , wherein the optical input comprises one of an edge coupler, a grating coupler, a graded index lens coupler, a fiber Bragg grating coupler, a micro-lens array coupler, an evanescent wave coupler, an adiabatic coupler, a wavelength division multiplexing coupler, a prism coupler, a butt coupler, an end-fire coupler, or a V-groove coupler.

6. The package of claim 5 , wherein the one or more optical fibers comprise a fiber array unit that is optically coupled to an edge coupler.

7. The package of claim 1 , wherein the photonic network is implemented using one or more waveguides.

8. The package of claim 1 , wherein the external device comprises one of a light engine or an electrical device.

9. The package of claim 1 , wherein one or more of the electrical interconnects comprise a redistribution layer.

10. The package of claim 9 , wherein the redistribution layer comprises one or more of electrical interconnections or through-glass vias between the dies and the bridging element.

11. The package of claim 1 , wherein the package substrate comprises a printed circuit board, an interposer, or a motherboard.

12. The package of claim 1 , wherein the first photonic transceiver or the second photonic transceiver comprises a modulator and a photodetector.

13. The package of claim 12 , wherein the modulator comprises one of a Mach-Zehnder interferometer, electro-absorption modulator, or a ring modulator.

14. The package of claim 12 , wherein the modulator is configured to modulate using one of a non-return-to-zero or a pulse amplitude modulation scheme.

15. The package of claim 12 , wherein the one or more AMS blocks are aligned with the dies such that the data serialization and deserialization interfaces are accessible by compute elements or memory regions disposed in central regions of the dies.

16. The package of claim 12 , wherein the one or more AMS blocks further comprise a modulator driver.

17. The package of claim 1 , wherein the one or more AMS blocks further comprise a transmit bonding engine and a receive bonding engine.

18. The package of claim 1 , wherein the one or more AMS blocks further comprise a transimpedance amplifier.

19. The package of claim 1 , wherein the one or more AMS blocks further comprise a slicer.

20. The package of claim 1 , wherein the one or more AMS blocks further comprise a gain control.

Assignees

• Celestial Ai Inc

Inventors

• Winterbottom Philip
• Lazovsky David
• Aggarwal Ankur
• Bos Martinus
• Sahni Subal

Classifications

• G01K7/023

  provided with specially adapted connectors (connectors per se H01R) · CPC title

• G02F1/0123 Primary

  Circuits for the control or stabilisation of the bias voltage, e.g. automatic bias control [ABC] feedback loops · CPC title

• G02F1/0157

  using electro-absorption effects, e.g. Franz-Keldysh [FK] effect or quantum confined stark effect [QCSE] · CPC title

• G01K7/14

  Arrangements for modifying the output characteristic, e.g. linearising · CPC title

• G01K7/028

  using microstructures, e.g. made of silicon · CPC title