Semiconductor device configured for gate dielectric monitoring

Patent metadata

Field	Value
Publication number	US-12442850-B2
Application number	US-202418734307-A
Country	US
Kind code	B2
Filing date	Jun 5, 2024
Priority date	Sep 9, 2019
Publication date	Oct 14, 2025
Grant date	Oct 14, 2025

Abstract

The disclosed technology relates generally to semiconductor devices, and more particularly to semiconductor devices including a metal-oxide-semiconductor (MOS) transistor and are configured for accelerating and monitoring degradation of the gate dielectric of the MOS transistor. In one aspect, a semiconductor device configured with gate dielectric monitoring capability comprises a metal-oxide-semiconductor (MOS) transistor including a source, a drain, a gate, and a backgate region formed in a semiconductor substrate. The semiconductor device additionally comprises a bipolar junction transistor (BJT) including a collector, a base, and an emitter formed in the semiconductor substrate, wherein the backgate region of the MOS transistor serves as the base of the BJT and is independently accessible for activating the BJT. The MOS transistor and the BJT are configured to be concurrently activated by biasing the backgate region independently from the source of the MOS transistor, such that the base of the BJT injects carriers of a first charge type into the backgate region of the MOS transistor, where the first charge type is opposite charge type to channel current carriers.

First claim

What is claimed is:

1. A method of monitoring a semiconductor device, the method comprising:
providing a semiconductor device comprising a metal-oxide-semiconductor (MOS) transistor comprising a source, a drain, a gate, and a backgate region, the semiconductor device further comprising a bipolar junction transistor (BJT) integrated on a same substrate with the MOS transistor, wherein a first well of a first dopant type forms the backgate region of the MOS transistor and serves as a base of the BJT and is independently accessible for activating the BJT, wherein the MOS transistor comprises an extended drain drift region comprising a second well of a second dopant type, opposite the first dopant type, between and abutting the drain and the first well; and
operating the semiconductor device in an accelerated stress mode in which a source voltage (V s ) applied to the source and a backgate voltage (V bg ) applied to the backgate region are different voltages.

2. The method of claim 1 , further comprising interchangeably operating the semiconductor device between the accelerated stress mode and a product mode, wherein in the product mode, the source and the backgate region are biased with a same voltage.

3. The method of claim 1 , wherein the MOS transistor is a double diffused metal-oxide-semiconductor (DMOS) transistor comprising the extended drain drift region covered by a field oxide between the drain and a channel of the DMOS transistor.

4. The method of claim 2 , wherein operating the semiconductor device in the accelerated stress mode further comprises:
activating the DMOS transistor by applying a gate voltage (V g ) to the gate that is greater in magnitude than the V s and the V bg , and further applying a drain voltage (V d ) to the drain; and
activating the BJT by applying the V bg that is greater in magnitude than the V s .

5. The method of claim 4 , wherein one or more of a difference between the V g and the V bg (V g −V bg ), a difference between the V g and the V d (V g −V d ) and a difference between the V d and the V bg (V d −V bg ) are kept substantially constant between the accelerated stress mode and the product mode.

6. A method of monitoring a semiconductor device, the method comprising:
activating a metal-oxide-semiconductor (MOS) transistor by inducing a conductive channel between a source and a drain of the MOS transistor under a gate bias; and
activating or deactivating a bipolar junction transistor (BJT) by applying a suitable bias to a backgate region of the MOS transistor, wherein a first well of a first dopant type forms the back gate region of the MOS transistor and serves as a base of the BJT and is independently accessible for activating the BJT, wherein the MOS transistor comprises an extended drain drift region comprising a second well of a second dopant type, opposite the first dopant type, between and abutting the drain and the first well, thereby injecting carriers of a first type to the backgate region, the carriers of the first type being opposite charge type to channel current carriers.

7. The method of claim 6 , wherein the MOS transistor is a double diffused metal-oxide-semiconductor (DMOS) transistor.

8. The method of claim 7 , wherein activating the DMOS transistor and activating the BJT comprises:
applying a drain voltage (V d ) to the drain of the DMOS transistor, wherein the drain is electrically connected to a collector of the BJT;
applying a backgate voltage (V bg ) to the backgate region of the DMOS transistor, wherein the backgate region of the DMOS serves as the base of the BJT; and
applying a source voltage (V s ) to a source of the DMOS transistor, wherein the source of the DMOS transistor serves as an emitter of the BJT, wherein the V bg and the V s are different.

9. The method of claim 8 , wherein deactivating the BJT comprises applying the same magnitude of the V bg and the V s .

10. The method of claim 9 , wherein one or more of a difference between the V g and the V bg (V g −V bg ), a difference between the V g and the V d (V g −V d ) and a difference between the V d and the V bg (V d −V bg ) are kept substantially constant between activating and deactivating the BJT.

11. The method of claim 8 , further comprising applying a gate voltage (V g ) to a gate of the DMOS transistor.

12. The method of claim 8 , wherein applying the V bg to the backgate region activates the BJT and injects the carriers of the first type to the backgate region.

13. The method of claim 8 , wherein the DMOS transistor is an n-channel DMOS transistor such that the carriers of the first type injected to the backgate region are holes.

14. The method of claim 8 , further comprising increasing the V bg to the backgate region to increase the carriers of the first type.

15. The method of claim 8 , further comprising applying a ground voltage to both the source and the backgate region of the DMOS transistor.

16. A method of operating a semiconductor device which includes a double diffused metal-oxide-semiconductor (DMOS) transistor, the method comprising:
providing a first well of a first dopant type forming a backgate region of the DMOS transistor, and an extended drain drift region of the DMOS transistor comprising a second well of a second dopant type, opposite the first dopant type, between and abutting a drain of the DMOS transistor and the first well;
activating the DMOS transistor by inducing a conductive channel between a source and the drain of the DMOS transistor under a gate bias; and
flowing a current of a first type of carrier through the conductive channel by applying a bias between the source and the drain, wherein by flowing the current of a first type of carrier, a current of a second type of carrier opposite the first charge type of the first type of carrier flows in the opposite direction, and wherein the current of the second type of carrier causes a failure of a gate dielectric of the DMOS transistor.

17. The method of claim 16 , wherein activating the DMOS transistor comprises:
applying a drain voltage (V d ) to the drain of the DMOS transistor;
applying a backgate voltage (V bg ) to the backgate region of the DMOS transistor;
applying a source voltage (V s ) to the source of the DMOS transistor, wherein the V s and the V bg are the same voltage; and
applying a gate voltage (V g ) to a gate of the DMOS transistor.

18. The method of claim 17 , further comprising activating a bipolar junction transistor (BJT) by applying the V bg that is higher in magnitude than the V s , wherein the backgate region of the DMOS transistor serves as a base of the BJT and is independently accessible for activating the BJT, thereby injecting carriers of the second type to the backgate region.

19. The method of claim 18 , wherein applying the voltage of the V bg and the V s deactivates the BJT.

20. The method of claim 19 , wherein one or more of a difference between the V g and the V bg (V g −V bg ), a difference between the V g and the V d (V g −V d ) and a difference between the V d and V bg (V d −V bg ) are kept substantially constant between activating and deactivating the BJT.

Assignees

• Analog Devices International Unlimited Co

Inventors

• Coyne Edward John
• Meskell John P
• Heffernan Colm Patrick
• Forde Mark
• Geary Shane

Classifications

• H10D30/603 Primary

  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS] · CPC title

• H10P74/277 Primary

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D84/409

  Combinations of FETs or IGBTs with lateral BJTs and with one or more of diodes, resistors or capacitors · CPC title

• H10D10/60

  Lateral BJTs · CPC title