Layered substrate structures with aligned optical access to electrical devices
US-2022158068-A1 · May 19, 2022 · US
Solder-shielded chip bonding
US12439834B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12439834-B2 |
| Application number | US-202218069996-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 21, 2022 |
| Priority date | Dec 21, 2022 |
| Publication date | Oct 7, 2025 |
| Grant date | Oct 7, 2025 |
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- Title
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Abstract
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A structure includes a first device having a first chip and a second chip. The second chip has a first side with a plurality of bumps and a second side with a plurality of first superconducting lines. A solder bonded layer attaches the first chip to the second chip. A second device has a first side with a plurality of pads facing the plurality of bumps in the second chip and a second side opposite the first side having a plurality of second superconducting lines. A solder shield material surrounds the plurality of bumps and the plurality of pads, and the plurality of bumps on the second chip are bonded to the plurality of pads on the second device. The solder shield material is connected to the plurality of first superconducting lines of the first device and to the plurality of second superconducting lines of the second device.
First claim
Opening claim text (preview).
What is claimed is: 1. A structure comprising: a first device comprising a first chip and a second chip, the second chip having a first side with a plurality of bumps and a second side having a plurality of first superconducting lines; a solder bonded layer attaching the first chip to a second side of the second chip opposite the first side; a second device having a first side with a plurality of pads facing the plurality of bumps in the second chip and a second side of the second device opposite the first side having a plurality of second superconducting lines; and a solder shield material surrounding the plurality of bumps and the plurality of pads, wherein the plurality of bumps on the second chip are bonded to the plurality of pads on the second device; and the solder shield material is connected to the plurality of first superconducting lines of the first device and to the plurality of second superconducting lines of the second device. 2. The structure according to claim 1 , wherein the second chip comprises a qubit chip. 3. The structure according to claim 2 , wherein: the first chip comprises a handler wafer having a first attachment surface including a first metal deposition layer; the qubit chip has a second attachment surface including a second metal deposition layer; and the first attachment surface of the handler wafer and the second attachment surface of the qubit chip are bonded by the solder bonding layer located between the first attachment surface and the second attachment surface. 4. The structure according to claim 1 , wherein the solder shield material comprises a superconducting material. 5. The structure according to claim 1 , wherein the second device has metal lines or planes inside layers. 6. The structure according to claim 5 , wherein the second device includes exit and entry points in the second superconducting lines sized for passage of microwave signals to the qubit chip. 7. The structure according to claim 5 , wherein the metal lines or planes within the second device comprises a superconducting material. 8. The structure according to claim 1 , wherein the plurality of bumps in the second chip comprises a superconducting material. 9. The structure according to claim 1 , further comprising a solder shield side wall having a first end disposed on the first device. 10. The structure according to claim 9 , wherein the solder shield side wall further comprises a second end connected to the second superconducting lines of the second device.
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- What does patent US12439834B2 cover?
- A structure includes a first device having a first chip and a second chip. The second chip has a first side with a plurality of bumps and a second side with a plurality of first superconducting lines. A solder bonded layer attaches the first chip to the second chip. A second device has a first side with a plurality of pads facing the plurality of bumps in the second chip and a second side oppos…
- Who is the assignee on this patent?
- IBM
- What technology area does this patent fall under?
- Primary CPC classification H10N60/82. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Oct 07 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 6 related publications on this page (citations in our corpus or others sharing the same primary CPC).