Light emitting device with electrode having specified molar ratio of magnesium to zinc

Patent metadata

Field	Value
Publication number	US-12439742-B2
Application number	US-201917280045-A
Country	US
Kind code	B2
Filing date	Sep 26, 2019
Priority date	Sep 26, 2018
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

A stacked body comprising: a semiconductor layer comprising a group III-V nitride semiconductor, and an electrode layer, wherein the electrode layer comprises magnesium oxide and zinc oxide, wherein the molar ratio of magnesium based on the sum of magnesium and zinc of the electrode layer [Mg/(Mg+Zn)] is 0.25 or more and 0.75 or less, and conductivity of the electrode layer is 1.0×10−2 S/cm or more.

First claim

The invention claimed is:

1. A stacked body, comprising:
a semiconductor layer comprising a group III-V nitride semiconductor; and
an electrode layer comprising magnesium oxide and zinc oxide,
wherein the electrode layer has regions mainly composed of zinc oxide and regions mainly composed of magnesium oxide,
wherein the electrode layer has a molar ratio of magnesium based on a sum of magnesium and zinc, Mg/(Mg+Zn), in a range of from 0.25 to 0.75, and the electrode layer has a conductivity of 1.0×10 −2 S/cm or more.

2. The stacked body according to claim 1 , wherein the molar ratio of magnesium based on the sum of magnesium and zinc of the electrode layer, Mg/(Mg+Zn), (Mg+Zn), is in a range of 0.4 to 0.75.

3. The stacked body according to claim 1 , wherein the molar ratio of magnesium based on the sum of magnesium and zinc of the electrode layer, Mg/(Mg+Zn), is in a range of 0.5 to 0.75.

4. The stacked body according to claim 1 , wherein the electrode layer further comprises trivalent or tetravalent element X other than Mg and Zn, and the electrode layer has a molar ratio of the trivalent or tetravalent element X based on total metal elements in a range of 0.0001 to 0.20.

5. The stacked body according to claim 4 , wherein the trivalent or tetravalent element X is at least one element selected from the group consisting of B, Al, Ga, In, Tl, C, Si, Ge, Sn and Pb.

6. The stacked body according to claim 1 , wherein in an X-ray diffraction measurement of the electrode layer, a diffraction peak is observed at 2θ=34.8±0.5 deg.

7. The stacked body according claim 1 , wherein the electrode layer has a light transmittance of 4% or more at a wavelength of 260 nm.

8. The stacked body according to claim 1 , wherein the electrode layer comprises microcrystals and is phase-separated.

9. The stacked body according to claim 1 , wherein the electrode layer has a columnar crystal growth.

10. The stacked body according to claim 1 , wherein a particle size of a region mainly of magnesium oxide of the electrode layer is from 20 nm to 200 nm.

11. The stacked body according to claim 1 , wherein the semiconductor layer comprises AlN, GaN, InN, or a mixed crystal thereof.

12. The stacked body according to claim 1 , further comprising:
a wiring layer in contact with a part of the electrode layer,
wherein the wiring layer comprises at least one selected from the group consisting of metals comprising one or more selected from Ni, Pd, Pt, Rh, Zn, In, Sn, Ag, Au, Mo, Ti, Cu and Al, oxides selected from ITO, SnO 2 , ZnO, In 2 O 3 , Ga 2 O 3 , RhO 2 , NiO, CoO, PdO, PtO, CuAlO 2 and CuGaO 2 , nitrides selected from TiN, TaN and SiNx, and poly-Si.

13. The stacked body according to claim 1 , wherein the electrode layer has a thickness of from 10 nm to 1 μm.

14. A semiconductor device, comprising the stacked body according to claim 1 .

15. A method, comprising:
producing the stacked body according to claim 1 ,
wherein the electrode layer comprising magnesium oxide and zinc oxide is formed on the semiconductor layer comprising the group III-V nitride semiconductor.

16. The method according to claim 15 , further comprising:
heat-treating the electrode layer at a temperature of 750° C. or higher.

17. The method according to claim 15 , further comprising:
forming a wiring layer in contact with a part of the electrode layer,
wherein the wiring layer comprises at least one selected from the group consisting of metals comprising one or more selected from Ni, Pd, Pt, Rh, Zn, In, Sn, Ag, Au, Mo, Ti, Cu and Al, oxides selected from ITO, SnO 2 , ZnO, In 2 O 3 , Ga 2 O 3 , RhO 2 , NiO, CoO, PdO, PtO, CuAlO 2 and CuGaO 2 , nitrides selected from TiN, TaN and SiNx, and poly-Si.

18. The method according to claim 17 , further comprising:
forming the wiring layer by sputtering using at least one selected from O 2 , Ar and N 2 as a sputtering gas, or evaporation.

19. The method according to claim 15 , further comprising:
forming the electrode layer by sputtering using at least one selected from O 2 , Ar and N 2 as a sputtering gas, or ion plating.

Assignees

• Idemitsu Kosan Co
• National Univ Corporation Tokai National Higher Education And Research System
• Nikkiso Co Ltd

Inventors

• Ueoka Yoshihiro
• Tomai Shigekazu
• Katsumata Satoshi
• Kushimoto Maki
• Deki Manato
• Honda Yoshio
• Amano Hiroshi

Classifications

• H10D64/011 Primary

  of electrodes ohmically coupled to a semiconductor · CPC title

• C23C14/082 Primary

  of alkaline earth metals · CPC title

• C23C14/34

  Sputtering · CPC title

• H10H20/857

  Interconnections, e.g. lead-frames, bond wires or solder balls · CPC title

• H10H20/825

  containing nitrogen, e.g. GaN · CPC title