Display substrate, manufacturing method therefor, and display apparatus

Patent metadata

Field	Value
Publication number	US-12439692-B2
Application number	US-202117795887-A
Country	US
Kind code	B2
Filing date	Sep 18, 2021
Priority date	Sep 18, 2021
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

A display substrate, a manufacturing method therefor, and a display apparatus are provided. The display substrate includes a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer disposed on an substrate. The first semiconductor layer includes active layers of a plurality of poly silicon transistors, the first conductive layer includes gates of a plurality of poly silicon transistors, a first electrode plate of a storage capacitor and a first scan signal line. The second conductive layer includes a second electrode plate of the storage capacitor. The second semiconductor layer includes active layers of a plurality of oxide transistors. The third conductive layer includes gates of the plurality of oxide transistors.

First claim

The invention claimed is:

1. A display substrate, wherein:
in a direction perpendicular to the display substrate, the display substrate comprises a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer that are sequentially disposed on a substrate;
the first semiconductor layer comprises active layers of a plurality of poly silicon transistors, the first conductive layer comprises gates of the plurality of poly silicon transistors, a first electrode plate of a storage capacitor and a first scan signal line, the second conductive layer comprises a second electrode plate of the storage capacitor, the second semiconductor layer comprises active layers of a plurality of oxide transistors, the third conductive layer comprises gates of the plurality of oxide transistors, the fourth conductive layer comprises first electrodes and second electrodes of the plurality of poly silicon transistors, and first electrodes and second electrodes of the plurality of oxide transistors, and the fifth conductive layer comprises a first power supply line and a data signal line;
in a direction parallel to the display substrate, the display substrate comprises a plurality of sub-pixels, and any two adjacent rows of sub-pixels are symmetrical in an extension direction of the first scan signal line; and
first power supply lines in two adjacent columns of sub-pixels are connected with each other to form an integrated structure.

2. The display substrate of claim 1 , wherein any two adjacent columns of sub-pixels are symmetrical along an extension direction of the data signal line.

3. The display substrate of claim 2 , wherein the first scan signal line comprises a first branch and a second branch, and the fifth conductive layer further comprises an anode connection electrode;
an orthographic projection of the first branch of the first scan signal line on the substrate is overlapped with an orthographic projection of the anode connection electrode on the substrate.

4. The display substrate of claim 1 , wherein the fourth conductive layer further comprises a first initial signal line and a second initial signal line; and
the plurality of poly silicon transistors comprise a drive transistor, a first reset transistor, and a second reset transistor, and the first reset transistor is configured to reset an anode of a light emitting element through the first initial signal line under control of the first scan signal line; the second reset transistor is configured to reset a gate of the drive transistor through the second initial signal line under control of a reset control signal line.

5. The display substrate of claim 4 , wherein the first scan signal line comprises a first branch and a second branch, and an n-th row of sub-pixels and an (n+1)-th row of sub-pixels are symmetrical along the first branch of the first scan signal line, wherein n is a natural number between 1 and N−1, and N is a quantity of a row of sub-pixels;
a first reset transistor in the n-th row of sub-pixels is connected with a first scan signal line in an n-th stage, and a second reset transistor in the n-th row of sub-pixels is connected with a reset control signal line in an (n−1)-th stage;
a first reset transistor in the (n+1)-th row of sub-pixels is connected with the first scan signal line in the n-th stage, and a second reset transistor in the (n+1)-th row of sub-pixels is connected with a reset control signal line in an (n+1)-th stage.

6. The display substrate of claim 4 , wherein the first reset transistor comprises a first reset active layer, the second reset transistor comprises a second reset active layer, an extension direction of a channel region of the first reset active layer is the same as an extension direction of the data signal line, and an extension direction of a channel region of the second reset active layer is different from the extension direction of the channel region of the first reset active layer.

7. The display substrate of claim 6 , wherein the display substrate comprises a plurality of repetitive units, at least one of the repetitive units comprises a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel, and the first reset active layer comprises a channel region and first region and second region disposed on both sides of the channel region;
the first semiconductor layer comprises a plurality of first connect blocks, shared by first reset transistors in the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel, as a first region of the first reset active layer within at least one of the repetitive units.

8. The display substrate of claim 7 , wherein the first conductive layer further comprises a first branch of the first scan signal line, and the first branch of the first scan signal line extending in a first direction;
the first branch of the first scan signal line is provided with an annular aperture structure that comprises a first connect strip and a second connect strip, and the first connect strip and the second connect strip form a first aperture that exposes the first connect block, and an orthographic projection of the first connect strip on the substrate is overlapped with an orthographic projection of the channel regions of the first reset active layers in the first sub-pixel and the second sub-pixel on the substrate, and an orthographic projection of the second connect strip on the substrate is overlapped with an orthographic projection of the channel regions of the first reset active layers in the third sub-pixel and the fourth sub-pixel on the substrate.

9. The display substrate of claim 8 , wherein
at least one of the repetitive units comprises an eighth via through which the first initial signal line is connected with the first connect block, and an orthographic projection of the first aperture on the substrate overlays with an orthographic projection of the eighth via on the substrate.

10. The display substrate of claim 7 , wherein the first conductive layer further comprises a reset control signal line, and the second reset active layer comprises the channel region and a first region and a second region disposed on both sides of the channel region;
the reset control signal line is disposed between two adjacent rows of repetitive units, and the reset control signal line extends in a first direction and is provided with a plurality of first bumps extending in a second direction or a direction opposite to the second direction, and the plurality of first bumps are overlapped with channel regions of the second reset active layers in the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel.

11. The display substrate of claim 10 , wherein
the second initial signal line is disposed between two adjacent rows of repetitive units, and the second initial signal line extends in the first direction and is provided with a plurality of second bumps extending in the second direction or a direction opposite to the second direction, and the plurality of second bumps are connected to first regions of the second reset active layers in the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel through a via in an insulating layer.

12. The display substrate of claim 11 , wherein an orthographic projection of the second initial signal line on the substrate is overlapped with an orthographic projection of the reset control signal line on the substrate.

13. The display substrate of claim 1 , wherein the first conductive layer further comprises

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Lu Hui
• Chen Yipeng
• Xie Shuai
• Fang Fei
• Li Shuo
• Tian Xuewei
• Shi Ling

Classifications

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/0221

  comprising manufacture, treatment or patterning of TFT semiconductor bodies · CPC title

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G2320/0247

  Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes · CPC title