Display panel and display apparatus

Patent metadata

Field	Value
Publication number	US-2021134917-A1
Application number	US-202117147309-A
Country	US
Kind code	A1
Filing date	Jan 12, 2021
Priority date	Oct 23, 2020
Publication date	May 6, 2021
Grant date	—

Abstract

Provided are a display panel and a display apparatus. The display panel includes a driving array layer having functional layers and insulation layers. The driving array layer includes a first transistor, a second transistor, a first capacitor including a first plate and a second plate, and a second capacitor including a third plate and a fourth plate. An active layer of the first transistor contains silicon, and an active layer of the second transistor contains oxide semiconductor. The first plate and the second plate are located in two of the functional layers, respectively, and the third plate and the fourth plate are located in two of the functional layers, respectively.

First claim

What is claimed is:

1 . A display panel, comprising a driving array layer having functional layers and insulation layers, the driving array layer comprising:
a first transistor, wherein the first transistor comprises a first active layer comprising silicon; a second transistor, wherein the second transistor comprises a second active layer comprising oxide semiconductor; a first capacitor comprising a first plate and a second plate; and a second capacitor comprising a third plate and a fourth plate, wherein the first plate and the second plate are located in two of the functional layers, respectively, and the third plate and the fourth plate are located in two of the functional layers, respectively.

2 . The display panel according to claim 1 , wherein the first capacitor has a greater capacitance than the second capacitor.

3 . The display panel according to claim 2 , wherein the driving array layer comprises a pixel circuit, wherein the pixel circuit comprises a driving transistor, the first capacitor and the second capacitor, wherein the first capacitor is connected between a first power signal terminal and a gate electrode of the driving transistor and is configured to store a signal transmitted to the gate electrode of the driving transistor.

4 . The display panel according to claim 2 , wherein the driving array layer comprises:
a pixel circuit comprising the first capacitor; and a driving circuit configured to provide a control signal to the pixel circuit and comprising the second capacitor.

5 . The display panel according to claim 2 , wherein the insulation layers comprise:
a first insulation layer provided between the first plate and the second plate; and a second insulation layer provided between the third plate and the fourth plate, wherein the first insulation layer has a greater hydrogen content than the second insulation layer.

6 . The display panel according to claim 5 , wherein the first insulation layer has a smaller oxygen content than the second insulation layer.

7 . The display panel according to claim 5 , wherein in at least one of the insulation layer provided between the third plate and the fourth plate, an oxygen content close to the third plate is greater than an oxygen content close to the fourth plate, and a hydrogen content close to the third plate is smaller than a hydrogen content close to the fourth plate.

8 . The display panel according to claim 4 , wherein the first plate and the third plate are located in one of the functional layers, and the second plate and the fourth plate are located in one of the functional layers, and
the insulation layers comprise a first insulation layer provided between the first plate and the second plate, and a second insulation layer is provided between the third plate and the fourth plate, wherein a hydrogen content of the first insulation layer is different from a hydrogen content of the second insulation layer.

9 . The display panel according to claim 4 , wherein the pixel circuit comprises the first transistor, and the driving circuit comprises the second transistor,
wherein an orthographic projection of the first capacitor on a plane of the display panel at least partially overlaps an orthographic projection of the first transistor of the pixel circuit on the plane of the display panel, and wherein an orthographic projection of the second capacitor on the plane of the display panel does not overlap an orthographic projection of the second transistor on the plane of the display panel.

10 . The display panel according to claim 4 , wherein the pixel circuit comprises the first transistor, and the driving circuit comprises the second transistor, and
an area of a region where an orthographic projection of the first capacitor on a plane of the display panel overlaps an orthographic projection of the first transistor of the pixel circuit on the plane of the display panel is greater than an area of a region where an orthographic projection of the second capacitor on the plane of the display panel overlaps an orthographic projection of the second transistor on the plane of the display panel.

11 . The display panel according to claim 4 , wherein the pixel circuit comprises the first transistor and a third transistor, and the driving circuit comprises the second transistor and a fourth transistor,
wherein the third transistor comprises a third active layer comprising oxide semiconductor, the fourth transistor comprises a fourth active layer comprising silicon, a channel region of the first transistor has a width of W1 and a length of L1; a channel region of the second transistor has a width of W2 and a length of L2; a channel region of the third transistor has a width of W3 and a length of L3; and a channel region of the fourth transistor has a width of W4 and a length of L4.

12 . The display panel according to claim 11 , wherein each of the first transistor and the third transistor is a switching transistor of the pixel circuit, where |W1/L1−W4/L4|<|W2/L2−W3/L3|.

13 . The display panel according to claim 11 , wherein the first transistor is a driving transistor of the pixel circuit, and the third transistor is a switching transistor of the pixel circuit, where |W1/L1−W4/L4|>5*|W2/L2−W3/L3|.

14 . The display panel according to claim 11 , wherein the first transistor is a switching transistor of the pixel circuit, and the third transistor is a driving transistor of the pixel circuit, where 5*|W1/L1−W4/L4|<|W2/L2−W3/L3|.

15 . The display panel according to claim 1 , further comprising:
a base substrate, wherein the driving array layer is disposed on the base substrate and comprises a first metal layer, a second metal layer, a third metal layer and a fourth metal layer that are sequentially arranged in a direction facing away from the base substrate; and wherein the first transistor comprises a first gate electrode, a first source electrode, a first drain electrode and the first active layer; the second transistor comprises a second gate electrode, a third gate electrode, a second source electrode, a second drain electrode and the second active layer; the first gate electrode is located in the first metal layer, the second gate electrode is located in the second metal layer, the third gate electrode is located in the third metal layer, and at least one of the first source electrode, the first drain electrode, the second source electrode or the second drain electrode is located in the fourth metal layer; and the first active layer is located at a side of the base substrate close to the first gate electrode, and the second active layer is located between the second gate electrode and the third gate electrode.

16 . The display panel according to claim 15 , wherein the first plate is located in the first metal layer, and the second plate is located in the second metal layer.

17 . The display panel according to claim 16 , wherein the driving array layer comprises a pixel circuit, and the first transistor is a driving transistor of the pixel circuit;
wherein the pixel circuit comprises the first capacitor connected between a first power signal terminal and a gate electrode of the driving transistor and configured to store a signal transmitted to the gate electrode of the driving transistor; and wherein the first gate electrode is reused as the first plate, and an orthographic projection of the first capacitor on a plane of the display panel partially overlaps an orthographic projection of the first transistor on the plane of the display panel.

1

Assignees

• Xiamen Tianma Micro Electronics Co Ltd

Inventors

• Li Jieliang
• Liu Jiaxian

Classifications

• H10K59/1216 Primary

  the pixel elements being capacitors · CPC title

• H10K59/1213

  the pixel elements being TFTs · CPC title

• H10K59/12 Primary

  Active-matrix OLED [AMOLED] displays · CPC title

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title

• H10D86/423 Primary

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title