Monolithic high side gallium nitride device with integrated capacitive level shifter circuits

Patent metadata

Field	Value
Publication number	US-12439682-B2
Application number	US-202218051799-A
Country	US
Kind code	B2
Filing date	Nov 1, 2022
Priority date	Nov 2, 2021
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

Monolithic high side GaN-based circuits using capacitors for level shifting. In one aspect, a power converter includes a GaN-based die, a switch formed on the GaN-based die and having a gate terminal, where the switch is arranged to be selectively conductive according to a driver signal applied to the gate terminal, a buffer circuit formed on the GaN-based die and arranged to receive an input signal and generate a corresponding differential output signal at a first output terminal and at a second output terminal, and a voltage level converter formed on the GaN-based die and having a first input terminal coupled to the first output terminal via a first capacitor and having a second input terminal coupled to the second output terminal via a second capacitor, where the first and second capacitors are formed on the GaN-based die, and the voltage level converter is arranged to generate the driver signal.

First claim

What is claimed is:

1. A power converter comprising:
a GaN-based die;
a switch formed on the GaN-based die and having a gate terminal, a source terminal and a drain terminal, wherein the switch is arranged to be selectively conductive according to a driver signal applied to the gate terminal;
a buffer circuit formed on the GaN-based die and arranged to receive an input signal and generate a corresponding differential output signal at a first output terminal and at a second output terminal; and
a voltage level converter formed on the GaN-based die and having a first input terminal coupled to the first output terminal via a first capacitor and having a second input terminal coupled to the second output terminal via a second capacitor, and wherein the first and second capacitors are formed on the GaN-based die, and wherein an output terminal of the voltage level converter is coupled to the gate terminal and arranged to generate the driver signal.

2. The power converter of claim 1 , wherein the input signal is referenced to a ground and the driver signal is referenced to a floating voltage.

3. The power converter of claim 1 , wherein the input signal is a pulse width modulated (PWM) signal.

4. The power converter of claim 1 , further comprising a comparator formed on the GaN-based die and coupled between the voltage level converter and the gate terminal.

5. The power converter of claim 4 , further comprising a latch circuit formed on the GaN-based die and coupled between the comparator and the gate terminal.

6. The power converter of claim 1 , wherein the first and second capacitors are metal-insulator-metal capacitors.

7. The power converter of claim 1 , wherein the switch, the buffer circuit, the voltage level converter and the first and second capacitors are formed monolithically.

8. A circuit comprising:
a GaN-based die;
a switch formed on the GaN-based die and having a gate terminal, a source terminal and a drain terminal, wherein the switch is arranged to be selectively conductive according to a driver signal applied to the gate terminal;
a buffer circuit formed on the GaN-based die and having an input terminal and an first output terminal, the buffer circuit arranged to receive an input signal at the input terminal and generate a first output signal at the first output terminal;
a capacitor formed on the GaN-based die and having a first input terminal and a second output terminal, the first input terminal coupled to the first output terminal and arranged to receive the first output signal and generate a second output signal at the second output terminal, wherein the first output signal is referenced to a ground at the second output signal is referenced to a floating voltage; and
a voltage level converter formed on the GaN-based die and coupled to the second output terminal and arranged to generate the driver signal.

9. The circuit of claim 8 , wherein the input signal is a pulse width modulated (PWM) signal.

10. The circuit of claim 8 , further comprising a comparator formed on the GaN-based die and coupled between the voltage level converter and the gate terminal.

11. The circuit of claim 10 , further comprising a latch circuit formed on the GaN-based die and coupled between the comparator and the gate terminal.

12. The circuit of claim 8 , wherein the capacitor is a metal-insulator-metal capacitor.

13. The circuit of claim 8 , wherein the switch, the buffer circuit, the voltage level converter and the capacitor are formed monolithically.

14. A power converter comprising:
a GaN-based die;
a switch formed on the GaN-based die and having a gate terminal, a source terminal and a drain terminal, wherein the switch is arranged to be selectively conductive according to a driver signal applied to the gate terminal;
a buffer circuit formed on the GaN-based die and arranged to receive an input signal and generate a corresponding differential output signal at a first output terminal and at a second output terminal; and
a voltage level converter formed on the GaN-based die and having a first input terminal coupled to the first output terminal via a first capacitor and having a second input terminal coupled to the second output terminal via a second capacitor;
wherein the differential output signal is referenced to a ground;
wherein the first and second capacitors are arranged to receive differential output signal and generate a second differential output signal that is referenced to a floating voltage; and
wherein an output terminal of the voltage level converter is coupled to the gate terminal and arranged to generate the driver signal.

15. The power converter of claim 14 , wherein the input signal is a pulse width modulated (PWM) signal.

16. The power converter of claim 14 , further comprising a comparator formed on the GaN-based die and coupled between the voltage level converter and the gate terminal.

17. The power converter of claim 16 , further comprising a latch circuit formed on the GaN-based die and coupled between the comparator and the gate terminal.

18. The power converter of claim 14 , wherein the first and second capacitors are metal-insulator-metal capacitors.

19. The power converter of claim 14 , wherein the switch, the buffer circuit, the voltage level converter and the first and second capacitors are formed monolithically.

20. The power converter of claim 14 , further comprising a positive dV/dt detector circuit coupled to the source terminal and a negative dV/dt detector circuit coupled to the drain terminal.

Assignees

• Navitas Semiconductor Ltd

Inventors

• Giandalia Marco
• Sharma Santosh
• Lee Jung Hee
• Kinzer Daniel M

Classifications

• H10D84/01

  Manufacture or treatment · CPC title

• H02M3/003

  Constructional details, e.g. physical layout, assembly, wiring or busbar connections · CPC title

• H02M1/08

  Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters · CPC title

• H10D84/811 Primary

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title

• H10D84/05

  using Group III-V technology · CPC title