Integrated level shifter

Patent metadata

Field	Value
Publication number	US-9570927-B2
Application number	US-201514728874-A
Country	US
Kind code	B2
Filing date	Jun 2, 2015
Priority date	Sep 16, 2014
Publication date	Feb 14, 2017
Grant date	Feb 14, 2017

Abstract

GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Both the high side and the low side devices may have one or more integrated control, support and logic functions. Some devices employ electro-static discharge circuits and features formed within the GaN-based devices to improve the reliability and performance of the half bridge power conversion circuits.

First claim

What is claimed is:

1. A level shift circuit comprising:
a GaN-based level shift transistor, comprising:
a gate connected to a gate terminal,
a drain connected to a drain terminal, and
a source connected to a source terminal,

wherein the level shift transistor is configured to receive an input referenced to a ground at the gate terminal and to generate an output at the drain terminal, wherein the output is referenced to a floating voltage, and
wherein at least a portion of the drain terminal is shielded from the substrate by a shield metal between the substrate and the portion of the drain terminal.

2. The semiconductor device of claim 1 , wherein the level shift transistor is operated with a pulsed input signal, and wherein a duration of the pulsed input signal is less than 100 nanoseconds.

3. The semiconductor device of claim 1 , wherein a channel width of the level shift transistor is less than 100 microns.

4. The semiconductor device of claim 1 , wherein the drain of the level shift transistor is less than 100 microns from a bond pad.

5. The semiconductor device of claim 1 , wherein the level shift transistor includes a source ohmic contact area connected to the source terminal, and the source terminal is connected to a metal pad that is immediately adjacent to the source terminal and is more than 100 times the source ohmic contact area.

6. The semiconductor device of claim 1 , wherein the level shift transistor includes a drain ohmic contact area connected to the drain terminal, and the drain terminal is connected to a metal pad that is immediately adjacent to the drain terminal and is more than 100 times the drain ohmic contact area.

7. The semiconductor device of claim 1 , The semiconductor device of claim 1 wherein the level shift transistor comprises a source area and a drain area and the source area does not encircle the drain area.

8. The semiconductor device of claim 1 , wherein the level shift transistor comprises an active region having a source area at a first end and a drain area at an opposing end.

9. The level shift circuit of claim 1 comprising a transistor having an Idsat to Qoss ratio greater than one ampere per nanocoulomb.

10. The level shift circuit of claim 1 comprising a first capacitance between the drain terminal and the floating voltage, wherein the first capacitance is configured to prevent a change of output state when the floating voltage changes voltage potential from ground to a maximum allowed voltage.

11. The level shift circuit of claim 1 comprising an electrically conductive circuit element coupled between the source and the ground.

12. The level shift circuit of claim 1 comprising an electrically conductive circuit element coupled between the drain and a positive side of a power source that is referenced to the floating voltage.

13. The level shift circuit of claim 1 comprising a first circuit portion disposed on a first GaN device and a second circuit portion disposed on a second GaN device.

14. The level shift circuit of claim 13 wherein the first circuit portion comprises the output and the second circuit portion comprises a receiver circuit, and a bond wire forms an electrical connection between the output and the receiver circuit.

15. The level shift circuit of claim 13 wherein at least one level shift transistor and all ground referenced circuit elements of the level shift circuit are disposed on the first GaN device.

16. The level shift circuit of claim 15 comprising a low side power switch disposed on the first GaN device.

17. The level shift circuit of claim 13 wherein the second circuit portion comprises an electrically conductive circuit element coupled between the drain and a positive side of a power source that is referenced to the floating voltage.

18. The shift circuit of claim 17 comprising a high side power switch integrated on the same device.

19. A level shift circuit comprising:
a GaN-based level shift transistor, comprising:
a gate connected to a gate terminal,
a drain connected to a drain terminal, and
a source connected to a source terminal,

wherein the level shift transistor is configured to receive an input referenced to a ground at the gate terminal and to generate an output at the drain terminal, wherein the output is referenced to a floating voltage; and
a resistive element between the source and the ground.

20. The level shift circuit of claim 19 , wherein the gate is configured to receive a pulsed input signal, and wherein a duration of the pulsed input signal is less than 100 nanoseconds.

21. A level shift circuit comprising:
a GaN-based level shift transistor, comprising:
a gate connected to a gate terminal,
a drain connected to a drain terminal, and
a source connected to a source terminal,

wherein the level shift transistor is configured to receive an input referenced to a ground at the gate terminal and to generate an output at the drain terminal, wherein the output is referenced to a floating voltage; and
a bond pad,
wherein the drain of the level shift transistor is less than 100 microns from the bond pad.

22. The level shift circuit of claim 21 , wherein the level shift transistor includes a source ohmic contact area connected to the source terminal, wherein the source terminal is connected to the bond pad, and wherein the bond pad is more than 100 times the source ohmic contact area.

23. The level shift circuit of claim 21 , wherein the level shift transistor includes a drain ohmic contact area connected to the drain terminal, wherein the drain terminal is connected to the bond pad, and wherein the bond pad is more than 100 times the drain ohmic contact area.

Assignees

• Navitas Semiconductor Inc

Inventors

• Kinzer Daniel M
• Sharma Santosh
• Zhang Ju Jason

Classifications

• H10W90/811

  Multiple chips on leadframes · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W70/481

  for devices being provided for in groups H10D8/00 - H10D48/00 · CPC title

• H10W70/411 Primary

  Chip-supporting parts, e.g. die pads · CPC title

• H10W42/80

  protecting against overcurrent or overload, e.g. fuses or shunts (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title