Semiconductor device including data storage pattern with improved retention characteristics

Patent metadata

Field	Value
Publication number	US-12439602-B2
Application number	US-202318094007-A
Country	US
Kind code	B2
Filing date	Jan 6, 2023
Priority date	Sep 6, 2019
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

A semiconductor device includes a lower structure; a stack structure including gate layers and interlayer insulating layers and having an opening; a vertical structure in the opening; a contact structure on the vertical structure; and a conductive line on the contact structure. The vertical structure includes an insulating core region, a channel semiconductor layer covering side and lower surfaces of the insulating core region, data storage patterns between the channel semiconductor layer and the gate layers and spaced apart from each other, a first dielectric layer, and a second dielectric layer. At least a portion of the first dielectric layer is between the data storage patterns and the gate layers, at least a portion of the second dielectric layer is between the data storage patterns and the channel semiconductor layer, and the insulating core region includes first convex portions having increased widths in regions facing the gate layers.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor substrate;
a peripheral circuit region on the semiconductor substrate;
a conductive layer on the peripheral circuit region;
a first polysilicon layer on the conductive layer;
a stack structure on the first polysilicon layer; and
a vertical structure penetrating through the stack structure and contacting at least one of the first polysilicon layer and the conductive layer,
wherein the stack structure includes a plurality of gate layers and a plurality of interlayer insulating layers alternately stacked on the first polysilicon layer,
wherein the vertical structure includes an insulating core region, a channel layer, and a plurality of data storage patterns,
wherein the insulating core region extends in a vertical direction, the vertical direction being perpendicular to an upper surface of the semiconductor substrate,
wherein the channel layer includes a first portion between the stack structure and the insulating core region and a second portion contacting the first polysilicon layer,
wherein the plurality of data storage patterns are between the channel layer and the plurality of gate layers in a horizontal direction parallel to the upper surface of the semiconductor substrate, and are spaced apart from each other in the vertical direction, and
wherein a lowermost data storage pattern among the plurality of data storage patterns is at a higher level than the first polysilicon layer.

2. The semiconductor device according to claim 1 ,
wherein at least one of an upper surface and a lower surface in each of the plurality of data storage patterns is a concave shape.

3. The semiconductor device according to claim 1 ,
wherein the insulating core region includes:
an upper core portion adjacent to the stack structure in a horizontal direction; and
a lower core portion adjacent to the first polysilicon layer in the horizontal direction,

wherein the horizontal direction is parallel to the upper surface of the semiconductor substrate,
wherein the lower core portion of the insulating core region includes:
a first lower portion;
an intermediate portion on the first lower portion; and
a first upper portion on the intermediate portion, and

wherein a maximum width of the intermediate portion is greater than a minimum width of each of the first lower portion and the first upper portion.

4. The semiconductor device according to claim 3 ,
wherein the insulating core region further includes:
a second lower portion below the first lower portion; and
a second upper portion on the first upper portion,

wherein a maximum width of the second upper portion is greater than the minimum width of the first upper portion, and
wherein a maximum width of the second lower portion is greater than the minimum width of the first lower portion.

5. The semiconductor device according to claim 1 , wherein the conductive layer includes at least one of polysilicon or metal.

6. The semiconductor device according to claim 1 ,
wherein a lower end of the vertical structure is at a lower level than an upper surface of the conductive layer, and
wherein the conductive layer contacts the first polysilicon layer and is spaced apart from the channel layer.

7. The semiconductor device according to claim 1 , further comprising:
a second polysilicon layer between the first polysilicon layer and the stack structure,
wherein a lower surface of the first polysilicon layer contacts an upper surface of the conductive layer,
wherein an upper surface of the first polysilicon layer contacts a lower surface of the second polysilicon layer, and
wherein the conductive layer and the second polysilicon layer are spaced apart from the channel layer.

8. The semiconductor device according to claim 7 ,
wherein the vertical structure further includes:
a first dielectric layer including a first upper dielectric portion; and
a second dielectric layer including a second upper dielectric portion,

wherein at least a portion of the first upper dielectric portion is between the plurality of data storage patterns and the channel layer, and
wherein at least a portion of the second upper dielectric portion is between the plurality of data storage patterns and the plurality of gate layers.

9. The semiconductor device according to claim 8 ,
wherein the first dielectric layer further includes a first lower dielectric portion below the first upper dielectric portion,
wherein the second dielectric layer further includes a second lower dielectric portion below the second upper dielectric portion,
wherein the first upper dielectric portion and the first lower dielectric portion are spaced apart from each other by the first polysilicon layer, and
wherein the second upper dielectric portion and the second lower dielectric portion are spaced apart from each other by the first polysilicon layer.

10. The semiconductor device according to claim 9 ,
wherein the first polysilicon layer includes:
a first polysilicon portion between the conductive layer and the second polysilicon layer; and
a second polysilicon portion between the second upper dielectric portion and the second lower dielectric portion, and

wherein a distance between an upper end of the second polysilicon portion and a lower end of the second polysilicon portion is greater than a distance between an upper surface of the first polysilicon portion and a lower surface of the first polysilicon portion.

11. The semiconductor device according to claim 9 , further comprising:
a substrate insulating layer between the conductive layer and the second lower dielectric portion,
wherein the first lower dielectric portion is between the second lower dielectric portion and a lower portion of the insulating core region.

12. The semiconductor device according to claim 1 ,
wherein each of the plurality of data storage patterns includes a first side surface facing a corresponding one of the plurality of gate layers, and a second side surface facing the channel layer, and
wherein at least a portion of the second side surface is a concave shape.

13. A semiconductor device comprising:
a first structure including a first substrate, a second substrate, and a peripheral circuit region between the first substrate and the second substrate;
a second structure including a plurality of gate layers and a plurality of interlayer insulating layers alternately stacked, and overlapping the first structure in a vertical direction perpendicular to an upper surface of the first substrate; and
a vertical structure penetrating through the second structure in the vertical direction and contacting the second substrate of the first structure,
wherein the vertical structure includes:
an insulating core region extending in the vertical direction;
a channel layer on a side surface of the insulating core region;
a first dielectric layer between the channel layer and the plurality of gate layers and the plurality of interlayer insulating layers of the second structure;
a second dielectric layer between the first dielectric layer and the plurality of gate layers, and between the first dielectric layer and the plurality of interlayer insulating layers of the second structure; and
a plurality of data storage patterns between the first dielectric layer and the second dielectric layer, and spaced apart from each other in the vertical direction,

wherein the plurality of data storage patterns are adjacent to the plurality of gate layers in a horizontal direction parallel to the upper surface of the first substrate,
wherein the plurality of data storage patterns include

Assignees

• Samsung Electronics Co Ltd

Inventors

• Son Younghwan
• Jeong Sanghoon
• Hong Sangjun
• Kang Seogoo
• Han Jeehoon

Classifications

• H10B43/35

  with cell select transistors, e.g. NAND · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title

• H10D30/025

  of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318) · CPC title

• H10D84/016

  the components including vertical IGFETs · CPC title

• H10D84/0144

  Manufacturing their gate insulating layers · CPC title