Semiconductor device and method for manufacturing same

US9997533B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9997533-B2
Application numberUS-201615071006-A
CountryUS
Kind codeB2
Filing dateMar 15, 2016
Priority dateOct 6, 2015
Publication dateJun 12, 2018
Grant dateJun 12, 2018

How to read this patent

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

According to one embodiment, the plurality of charge storage films are separated in a stacking direction with a second air gap interposed. The plurality of insulating films are provided on side surfaces of electrode layers opposing the charge storage films, on portions of surfaces of the electrode layers continuous from the side surfaces and opposing a first air gap between the electrode layers, and on corners of the electrode layers between the portions and the side surfaces. The plurality of insulating films are divided in the stacking direction with a third air gap interposed and without the charge storage films being interposed. The third air gap communicates with the first air gap and the second air gap between the first air gap and the second air gap.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for manufacturing a semiconductor device, comprising: making a first through-portion in a stacked body, the first through-portion extending in a stacking direction, the stacked body including a first layer, a second layer, and a sacrificial layer provided between the first layer and the second layer; making a first gap while causing one portion of the sacrificial layer to remain between the first layer and the second layer by etching the sacrificial layer through the first through-portion, the first gap communicating with the first through-portion; forming a first film and causing a second gap to remain on an inner side of the first film, the first film being formed along a surface of the first layer adjacent to the first through-portion, along a surface of the first layer adjacent to the first gap, along a surface of the one portion of the sacrificial layer adjacent to the first gap, along a surface of the second layer adjacent to the first gap, and along a surface of the second layer adjacent to the first through-portion, the second gap communicating with the first through-portion; forming a second film in the second gap and on a side surface of the first film adjacent to the first through-portion; making a second through-portion in a region of the stacked body where the one portion of the sacrificial layer remains, the second through-portion extending in the stacking direction; exposing a first portion of the second film by etching the first film through the second through-portion, the first portion being formed in the second gap; and dividing the second film in the stacking direction by causing etching of at least a portion of the first portion of the second film to progress from an exposed portion of the first portion through the second through-portion. 2. The method for manufacturing the semiconductor device according to claim 1 , wherein the second through-portion is formed to expose a side surface of the one portion of the sacrificial layer in the second through-portion; and the first film is exposed prior to the etching the first film by etching the one portion of the sacrificial layer from the second through-portion. 3. The method for manufacturing the semiconductor device according to claim 1 , wherein the first film includes a first corner and a second corner in a state prior to the etching of the second film, a position of the first corner corresponding to a corner of the first layer, a position of the second corner corresponding to a corner of the second layer, the first portion of the second film being interposed between the first corner and the second corner in the stacking direction, and the first corner and the second corner of the first film remain after the etching of the second film. 4. The method for manufacturing the semiconductor device according to claim 3 , wherein the first corner and the second corner of the first film are adjacent to a region between a plurality of portions of the second films separated in the stacking direction. 5. The method for manufacturing the semiconductor device according to claim 3 , wherein the second film divided in the stacking direction covers the first corner and the second corner of the first film. 6. The method for manufacturing the semiconductor device according to claim 3 , further comprising removing, by etching, the first corner and the second corner of the first film remaining after the etching of the second film.

Assignees

Inventors

Classifications

  • by chemical means · CPC title

  • the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

  • the material being a silicon oxide, e.g. SiO2 · CPC title

  • of air gaps · CPC title

  • Air gaps · CPC title

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Frequently asked questions

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What does patent US9997533B2 cover?
According to one embodiment, the plurality of charge storage films are separated in a stacking direction with a second air gap interposed. The plurality of insulating films are provided on side surfaces of electrode layers opposing the charge storage films, on portions of surfaces of the electrode layers continuous from the side surfaces and opposing a first air gap between the electrode layers…
Who is the assignee on this patent?
Toshiba Memory Corp
What technology area does this patent fall under?
Primary CPC classification H01L27/11582. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jun 12 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).