Package substrate and semiconductor package including the same

Patent metadata

Field	Value
Publication number	US-12438134-B2
Application number	US-202217862586-A
Country	US
Kind code	B2
Filing date	Jul 12, 2022
Priority date	Oct 27, 2021
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

A semiconductor package includes a package substrate including a base substrate including a redistribution layer, pads disposed on first and second surfaces of the base substrate and connected to the redistribution layer, and a protective layer having a mounting region in which first openings respectively exposing first pads among the pads and a second opening exposing second pads among the pads and a portion of the second surface are disposed on the second surface; a semiconductor chip disposed on the mounting region and connected to the pads through the first openings and the second opening; and a sealing material covering a portion of the semiconductor chip and extending into the second opening. Four first openings among the first openings are respectively disposed adjacent to respective corners of the mounting region. The second opening is disposed to divide the four first openings into at least two groups.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a package substrate including:
a base substrate including a redistribution layer and having a front surface and a rear surface opposite to the front surface,
front pads disposed on the front surface and electrically connected to the redistribution layer,
rear pads disposed on the rear surface and electrically connected to the redistribution layer, and the rear pads including first rear pads and second rear pads,
a front protective layer including front openings respectively exposing the front pads on the front surface, and
a rear protective layer including a mounting region in which first rear openings respectively exposing the first rear pads and a second rear opening exposing the second rear pads and a portion of the rear surface are disposed on the rear surface;

a semiconductor chip disposed on the front protective layer and connected to the front pads;
a passive device disposed on the mounting region of the rear protective layer, and connected to the rear pads;
connection bumps disposed on the rear surface adjacent to the passive device, and electrically connected to the redistribution layer; and
a sealing material spaced apart from the connection bumps, covering a portion of the passive device, and extending into the second rear opening,
wherein four first rear openings of the first rear openings are respectively disposed adjacent to respective corners of the mounting region,
wherein the second rear opening is disposed to divide the four first rear openings into at least two groups,
wherein the first rear openings and the second rear opening are included in the mounting region, and
wherein the first rear pads corresponding to the first rear openings and the second rear pads corresponding to the second rear opening are disposed in the mounting region.

2. The semiconductor package of claim 1 , wherein the mounting region comprises:
first regions adjacent to the respective corners and respectively including at least one of the four first rear openings; and
a second region dividing the first regions and corresponding to the second rear opening.

3. The semiconductor package of claim 2 , wherein the first regions have the same shape as each other.

4. The semiconductor package of claim 1 , wherein the passive device has a top surface facing the mounting region and on which a connection terminal is disposed, a bottom surface opposite to the top surface, and side surfaces positioned between the top surface and the bottom surface.

5. The semiconductor package of claim 4 , wherein the mounting region has first to fourth edges connecting the respective corners, and
wherein the first to fourth edges correspond to the side surfaces of the passive device, respectively.

6. The semiconductor package of claim 5 , wherein the second rear opening has a side surface overlapping at least two of the first to fourth edges.

7. The semiconductor package of claim 5 , wherein the second rear opening further comprises an extended region extending outwardly of at least one of the first to fourth edges of the mounting region, and
wherein the sealing material extends into the extended region.

8. The semiconductor package of claim 7 , wherein the extended region surrounds the first to fourth edges of the mounting region.

9. The semiconductor package of claim 4 , wherein the passive device further comprises a connection member electrically connecting the connection terminal to the rear pads, and
wherein the connection member comprises a pillar portion in contact with the connection terminal and a solder portion connecting the pillar portion to the rear pads.

10. The semiconductor package of claim 1 , further comprising:
connection pads disposed on the rear surface and contacting the connection bumps; and
connection openings respectively exposing the connection pads on the rear surface,
wherein the connection bumps are electrically connected to the redistribution layer through the connection openings.

11. The semiconductor package of claim 10 , wherein each of the connection pads has a width greater than a width of each of the rear pads in a first direction.

12. The semiconductor package of claim 10 , wherein the connection pads are disposed at a different level from the rear pads.

13. The semiconductor package of claim 1 , wherein the rear pads are disposed in rows and columns, and have the same size as each other.

14. The semiconductor package of claim 1 , wherein the passive device comprises a capacitor.

15. The semiconductor package of claim 1 , wherein the passive device has the maximum height smaller than the maximum height of the connection bumps in a direction perpendicular to the rear surface.

16. The semiconductor package of claim 1 , further comprising:
an encapsulant sealing at least a portion of the semiconductor chip on the front protective layer.

17. A semiconductor package, comprising:
a package substrate including:
a base substrate including a redistribution layer,
a plurality of pads disposed on a first surface of the base substrate and electrically connected to the redistribution layer, and
a protective layer having a mounting region in which first openings respectively exposing first pads among the plurality of pads and a second opening exposing second pads among the plurality of pads and a portion of the first surface are disposed on the first surface of the base substrate;
a passive device disposed on the mounting region of the protective layer and electrically connected to the plurality of pads through the first openings and the second opening; and
a sealing material covering a portion of the passive device and extending into the second opening,
wherein four first openings among the first openings are respectively disposed adjacent to respective corners of the mounting region,
wherein the second opening is disposed to divide the four first openings into at least two groups,
wherein the first openings and the second opening are included in the mounting region and
wherein the first pads corresponding to the first openings and the second pads corresponding to the second opening are disposed in the mounting region.

18. The semiconductor package of claim 17 , wherein the passive device comprises a silicon (Si) capacitor.

19. A package substrate, comprising:
a base substrate including a plurality of insulating layers and redistribution layers disposed in the plurality of insulating layers, and having a front surface and a rear surface opposite to the front surface;
front pads disposed on the front surface and electrically connected to the redistribution layers;
rear pads disposed on the rear surface and electrically connected to the redistribution layers;
a front protective layer having front openings respectively exposing the front pads on the front surface; and
a rear protective layer having a mounting region in which first rear openings respectively exposing first rear pads among the rear pads and a second rear opening exposing second rear pads among the rear pads and a portion of the rear surface are disposed on the rear surface,
wherein four rear openings among the first rear openings are respectively disposed adjacent to respective corners of the mounting region,
wherein the second rear opening is disposed to divide the four rear openings into at least two groups,
wherein the first rear openings and the second rear opening are included in the mounting region, and
wherein the first rear pads corresponding to the first rear o

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Junwoo
• Kim Sangsoo
• Kim Seunghwan
• Kim Jungjoo
• Lee Yongkwan

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title