Wiring substrate

Patent metadata

Field	Value
Publication number	US-9627309-B2
Application number	US-201615138469-A
Country	US
Kind code	B2
Filing date	Apr 26, 2016
Priority date	Apr 28, 2015
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

A wiring substrate includes a first wiring substrate, a first insulation layer stacked on the first wiring layer, and second and third insulation layers sequentially stacked on the first insulation layer. An electronic component is mounted on the first insulation layer in a cavity extending through the second and third insulation layers. The cavity is filled with a fourth insulation layer that entirely covers an upper surface of the third insulation layer and covers the electronic component. A second wiring layer is incorporated in the second and third insulation layers and electrically connected to the first wiring layer. The second wiring layer is electrically connected to a third wiring layer, which is stacked on the fourth insulation layer, by a first via wiring extending through the second and third insulation layers.

First claim

The invention claimed is:

1. A wiring substrate comprising:
a first wiring layer;
a first insulation layer stacked on the first wiring layer;
a plurality of insulation layers including a second insulation layer, which is stacked on an upper surface of the first insulation layer, and a third insulation layer, which is stacked on an upper surface of the second insulation layer;
a cavity that extends through the plurality of insulation layers and partially exposes the upper surface of the first insulation layer;
an electronic component mounted on the first insulation layer exposed in the cavity;
a fourth insulation layer that entirely covers an upper surface of an uppermost one of the plurality of insulation layers and covers the electronic component, wherein the cavity is filled with the fourth insulation layer;
a second wiring layer electrically connected to the first wiring layer, incorporated in the plurality of insulation layers, and covered by the uppermost one of the plurality of insulation layers, wherein the second wiring layer is formed on the upper surface of the second insulation layer;
a first via wiring formed by a single via wiring, wherein the first via wiring extends continuously through the uppermost one of the plurality of insulation layers and the fourth insulation layer from an upper surface of the fourth insulation layer to an upper surface of the second wiring layer; and
a third wiring layer stacked on the upper surface of the fourth insulation layer and electrically connected to the second wiring layer by the first via wiring,
wherein the upper surface of the uppermost one of the plurality of insulation layers is free from a wiring layer.

2. The wiring substrate according to claim 1 , wherein
the plurality of insulation layers include the second insulation layer and the third insulation layer, and
the cavity extends through the second insulation layer and the third insulation layer in a thickness-wise direction,
the wiring substrate further comprising:
a second via wiring that extends through the first insulation layer;
a fourth wiring layer stacked on the upper surface of the first insulation layer and electrically connected to the first wiring layer by the second via wiring; and
a third via wiring that extends through the second insulation layer,
wherein the second wiring layer is electrically connected to the fourth wiring layer by the third via wiring, and
the third wiring layer is electrically connected to the second wiring layer by the first via wiring, the first via wiring extending through the third insulation layer and the fourth insulation layer.

3. The wiring substrate according to claim 1 , wherein
the plurality of insulation layers include the second insulation layer and the third insulation layer, and
the cavity extends through the second insulation layer and the third insulation layer in a thickness-wise direction,
the wiring substrate further comprising:
a fourth via wiring that extends through the first insulation layer and the second insulation layer,
wherein the second wiring layer is electrically connected to the first wiring layer by the fourth via wiring, and
the third wiring layer is electrically connected to the second wiring layer by the first via wiring, the first via wiring extending through the third insulation layer and the fourth insulation layer.

4. The wiring substrate according to claim 1 , wherein
the first wiring layer is a lowermost wiring layer, and
the first insulation layer covers an upper surface and a side surface of the first wiring layer and exposes a lower surface of the first wiring layer.

5. The wiring substrate according to claim 1 , further comprising a fifth wiring layer directly stacked on a lower surface of the first wiring layer and directly connected to the first wiring layer.

6. The wiring substrate according to claim 1 , further comprising a fifth via wiring with which a first through hole extending through the fourth insulation layer is filled, wherein the fifth via wiring is connected to the electronic component.

7. The wiring substrate according to claim 1 , further comprising a sixth via wiring with which a second through hole extending through the first insulation layer is filled, wherein the sixth via wiring is connected to the electronic component.

8. The wiring substrate according to claim 1 , further comprising:
a fifth via wiring with which a first through hole extending through the fourth insulation layer is filled;
a sixth wiring layer stacked on the upper surface of the fourth insulation layer and electrically connected to the electronic component by the fifth via wiring;
a sixth via wiring with which a second through hole extending through the first insulation layer is filled; and
a seventh wiring layer electrically connected to the electronic component by the sixth via wiring and stacked on at least one of a lower surface of the first insulation layer and a lower surface of the first wiring layer,
wherein the first through hole includes a first opening end located closer to the electronic component and a second opening end located closer to the upper surface of the fourth insulation layer, and the first opening end has a smaller diameter than the second opening end, and
the second through hole includes a third opening end located closer to the electronic component and a fourth opening end located closer to the lower surface of the first insulation layer, and the third opening end has a smaller diameter than the fourth opening end.

Assignees

• Shinko Electric Ind Co

Inventors

• Kobayashi Kazuhiro
• Sato Junji
• Kusama Yasuhiko

Classifications

• H05K2201/10015

  Non-printed capacitor · CPC title

• H05K3/4682

  Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil · CPC title

• H05K1/186

  manufactured by mounting on or connecting to patterned circuits before or during embedding · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title