Underfill control structures and method

Patent metadata

Field	Value
Publication number	US-9842788-B2
Application number	US-201615058699-A
Country	US
Kind code	B2
Filing date	Mar 2, 2016
Priority date	Dec 31, 2015
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

A semiconductor device and method of reducing the risk of underbump metallization poisoning from the application of underfill material is provided. In an embodiment a spacer is located between a first underbump metallization and a second underbump metallization. When an underfill material is dispensed between the first underbump metallization and the second underbump metallization, the spacer prevents the underfill material from creeping towards the second underbump metallization. In another embodiment a passivation layer is used to inhibit the flow of underfill material as the underfill material is being dispensed.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
forming a first underbump metallization and a second underbump metallization over a substrate, wherein the first underbump metallization is adjacent to the second underbump metallization;
forming a first spacer between the first underbump metallization and the second underbump metallization, wherein the forming the first underbump metallization and the forming the first spacer are performed simultaneously;
bonding a surface device to the first underbump metallization, wherein the surface device has a first surface facing the second underbump metallization; and
dispensing an underfill adjacent to the first surface, wherein the first spacer prevents the underfill from contacting the second underbump metallization, wherein the forming the first spacer further comprises forming a discontinuous spacer surrounding the first underbump metallization.

2. The method of claim 1 , wherein the forming the first spacer further comprises forming the first spacer surrounding the first underbump metallization.

3. The method of claim 1 , further comprising forming an opening within the substrate, wherein after the forming the first spacer and after the forming the opening the opening is located between the first spacer and the first underbump metallization.

4. A method of manufacturing a semiconductor device, the method comprising:
forming a redistribution layer over a semiconductor die, the redistribution layer comprising a first portion and a second portion;
depositing a passivation layer over the redistribution layer;
patterning the passivation layer to form a first opening over the first portion and a second opening over the second portion;
bonding a first surface device to the second portion through the second opening;
placing a first external connection in electrical connection with the first portion through the first opening; and
dispensing an underfill material into the second opening and between the first surface device and the semiconductor die.

5. The method of claim 4 , further comprising forming an underbump metallization within the first opening prior to the placing the first external connection.

6. The method of claim 4 , wherein the placing the first external connection places the first external connection in direct physical contact with the first portion of the redistribution layer.

7. The method of claim 4 , wherein the dispensing the underfill material places the underfill material in physical contact with a third portion of the redistribution layer that is unconnected to the first surface device.

8. The method of claim 4 , wherein the passivation layer blocks movement of the underfill material during the dispensing the underfill material.

9. The method of claim 4 , further comprising encapsulating the semiconductor die with an encapsulant prior to the forming the redistribution layer.

10. The method of claim 9 , wherein the encapsulating the semiconductor die further encapsulates a via that is separated from the semiconductor die.

11. The method of claim 10 , further comprising planarizing the encapsulant, the via, and the semiconductor die prior to the forming the redistribution layer.

12. A method of manufacturing a semiconductor device, the method comprising:
forming a first spacer over a semiconductor substrate between a first underbump metallization and a second underbump metallization, wherein the forming the first spacer forms a discontinuous spacer;
after the forming the first spacer, bonding a surface device to the first underbump metallization;
forming a first external connector to the second underbump metallization;
dispensing an underfill material between the first spacer and the first underbump metallization, wherein the first spacer prevents the underfill material from contacting the second underbump metallization.

13. The method of claim 12 , further comprising:
a passivation layer between the semiconductor substrate and the surface device; and
an opening in the passivation layer, wherein the dispensing the underfill material at least partially fills the opening.

14. The method of claim 13 , wherein the opening exposes a conductive layer between the passivation layer and the semiconductor substrate.

15. The method of claim 12 , further comprising a second spacer located between the first spacer and the second underbump metallization.

16. The method of claim 15 , further comprising a second surface device adjacent to the first surface device.

17. The method of claim 12 , wherein the first spacer is located along a single side of the surface device.

18. The method of claim 3 , wherein the dispensing the underfill places at least a portion of the underfill into the opening.

19. The method of claim 1 , further comprising forming a second spacer adjacent to the first spacer.

20. The method of claim 1 , further comprising bonding a second surface device adjacent to the surface device.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Ying-Ju
• Su An-Jhih
• Chen Hsien-Wei
• Yeh Der-Chyang
• Wu Chi-Hsi
• Yu Chen-Hua

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W72/387

  Flow barriers · CPC title