Driving method of semiconductor device

Patent metadata

Field	Value
Publication number	US-12437793-B2
Application number	US-202118245784-A
Country	US
Kind code	B2
Filing date	Sep 9, 2021
Priority date	Sep 22, 2020
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

A semiconductor device with high reliability is provided. The semiconductor device includes a memory cell including a first ferroelectric capacitor and a reference memory cell including a second ferroelectric capacitor. In a first period, first binary data is written to the memory cell, and first reference binary data is written to the reference memory cell. In a second period, the first binary data is read from the memory cell, and the first reference binary data is read from the reference memory cell. In a third period, logic operation of the first binary data and the first reference binary data is performed. In a fourth period, second binary data is written to the memory cell, and second reference binary data is written to the reference memory cell. A value of the first binary data and a value of the second binary data are different from each other, and a value of the first reference binary data and a value of the second reference binary data are different from each other.

First claim

The invention claimed is:

1. A method for driving a semiconductor device comprising a memory cell comprising a ferroelectric capacitor, comprising:
writing binary data to the memory cell in a first period;
reading the binary data from the memory cell in a second period; and
generating a polarization reversal in the ferroelectric capacitor in a third period, so that the binary data is returned to the memory cell,
wherein the memory cell comprises a first transistor, a second transistor, and a third transistor,
wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and one electrode of the ferroelectric capacitor,
wherein one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the third transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the first transistor,
wherein in the first period and the third period, the first transistor is in an on state and the third transistor is in an off state, and
wherein in the second period, the first transistor is in an off state and the third transistor is in an on state.

2. The method for driving a semiconductor device according to claim 1 , wherein in the third period, the polarization reversal is generated in the ferroelectric capacitor regardless of a value of the binary data.

3. The method for driving a semiconductor device according to claim 2 ,
wherein the ferroelectric capacitor comprises a dielectric, and
wherein the dielectric comprises at least one of hafnium oxide and zirconium oxide.

4. The method for driving a semiconductor device according to claim 1 ,
wherein the semiconductor device further comprises a reference memory cell,
wherein reference binary data is written to the reference memory cell in the first period,
wherein the reference binary data is read from the reference memory cell in the second period, and
wherein logic operation of the binary data read from the memory cell and the reference binary data read from the reference memory cell is performed in the second period.

5. The method for driving a semiconductor device according to claim 4 , wherein the logic operation is exclusive disjunction.

6. The method for driving a semiconductor device according to claim 5 ,
wherein the ferroelectric capacitor comprises a dielectric, and
wherein the dielectric comprises at least one of hafnium oxide and zirconium oxide.

7. The method for driving a semiconductor device according to claim 4 ,
wherein the ferroelectric capacitor comprises a dielectric, and
wherein the dielectric comprises at least one of hafnium oxide and zirconium oxide.

8. The method for driving a semiconductor device according to claim 1 ,
wherein the ferroelectric capacitor comprises a dielectric, and
wherein the dielectric comprises hafnium oxide and/or zirconium oxide.

9. A method for driving a semiconductor device comprising a memory cell comprising a first ferroelectric capacitor and a reference memory cell comprising a second ferroelectric capacitor, comprising:
writing first binary data to the memory cell and writing first reference binary data to the reference memory cell in a first period;
reading the first binary data from the memory cell and reading the first reference binary data from the reference memory cell in a second period;
performing logic operation of the first binary data and the first reference binary data in a third period; and
writing second binary data to the memory cell and writing second reference binary data to the reference memory cell in a fourth period,
wherein a value of the first binary data and a value of the second binary data are different from each other, and
wherein a value of the first reference binary data and a value of the second reference binary data are different from each other.

10. The method for driving a semiconductor device according to claim 9 ,
wherein the semiconductor device comprises a first sense amplifier circuit and a second sense amplifier circuit,
wherein the first sense amplifier circuit is electrically connected to the memory cell,
wherein the second sense amplifier circuit is electrically connected to the reference memory cell, and
wherein in the third period, the first sense amplifier circuit and the second sense amplifier circuit are each in an activation state.

11. The method for driving a semiconductor device according to claim 10 ,
wherein the memory cell comprises a first transistor, a second transistor, and a third transistor,
wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and one electrode of the first ferroelectric capacitor,
wherein one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the third transistor,
wherein the other of the source and the drain of the first transistor and the other of the source and the drain of the third transistor are electrically connected to the first sense amplifier circuit,
wherein in the first period and the fourth period, the first transistor is in an on state and the third transistor is in an off state, and
wherein in the second period and the third period, the first transistor is in an off state and the third transistor is in an on state.

12. The method for driving a semiconductor device according to claim 11 ,
wherein the first ferroelectric capacitor comprises a first dielectric,
wherein the second ferroelectric capacitor comprises a second dielectric, and
wherein the first dielectric and the second dielectric each comprise at least one of hafnium oxide and zirconium oxide.

13. The method for driving a semiconductor device according to claim 11 , wherein the logic operation is exclusive disjunction.

14. The method for driving a semiconductor device according to claim 10 ,
wherein the first ferroelectric capacitor comprises a first dielectric,
wherein the second ferroelectric capacitor comprises a second dielectric, and
wherein the first dielectric and the second dielectric each comprise at least one of hafnium oxide and zirconium oxide.

15. The method for driving a semiconductor device according to claim 10 , wherein the logic operation is exclusive disjunction.

16. The method for driving a semiconductor device according to claim 9 ,
wherein the first ferroelectric capacitor comprises a first dielectric,
wherein the second ferroelectric capacitor comprises a second dielectric, and
wherein the first dielectric and the second dielectric each comprise hafnium oxide and/or zirconium oxide.

17. The method for driving a semiconductor device according to claim 16 , wherein the logic operation is exclusive disjunction.

18. The method for driving a semiconductor device according to claim 9 , wherein the logic operation is exclusive disjunction.

Assignees

• Semiconductor Energy Lab

Inventors

• Okamoto Yuki
• Onuki tatsuya
• Matsuzaki Takanori

Classifications

• G11C11/2293

  Timing circuits or methods · CPC title

• G11C11/2273

  Reading or sensing circuits or methods · CPC title

• G11C11/221 Primary

  using ferroelectric capacitors · CPC title

• G11C11/2259

  Cell access · CPC title

• G11C11/2275 Primary

  Writing or programming circuits or methods · CPC title