Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10121705-B2
Application number	US-201414469920-A
Country	US
Kind code	B2
Filing date	Aug 27, 2014
Priority date	Nov 21, 2013
Publication date	Nov 6, 2018
Grant date	Nov 6, 2018

Abstract

To suppress performance degradation of a semiconductor device, when the width of a first active region having a first field effect transistor formed therein is smaller than the width of a second active region having a second field effect transistor formed therein, the height of a surface of a first raised source layer of the first field effect transistor is made larger than the height of a surface of a second raised source layer of the second field effect transistor. Moreover, the height of a first surface of a raised drain layer of the first field effect transistor is made larger than a surface of a second raised drain layer of the second field effect transistor.

First claim

What is claimed is:

1. A semiconductor device comprising:
(a) a first field effect transistor formed in a first active region; and
(b) a second field effect transistor formed in a second active region,
wherein the first field effect transistor includes:
(a1) a first source region and a first drain region which are formed in the first active region so as to be mutually spaced apart from each other;
(a2) a first channel region sandwiched between the first source region and the first drain region;
(a3) a first gate insulating film formed on the first channel region;
(a4) a first gate electrode formed on the first gate insulating film;
(a5) a first raised source layer formed on the first source region; and
(a6) a first raised drain layer formed on the first drain region,

wherein the second field effect transistor includes:
(b1) a second source region and a second drain region which are formed in the second active region so as to be mutually spaced apart from each other;
(b2) a second channel region sandwiched between the second source region and the second drain region;
(b3) a second gate insulating film formed on the second channel region;
(b4) a second gate electrode formed on the second gate insulating film;
(b5) a second raised source layer formed on the second source region; and
(b6) a second raised drain layer formed on the second drain region,

wherein the first active region has a width in a gate width direction of the first gate electrode that is smaller than a width of the second active region in a gate width direction of the second gate electrode,
wherein, in a cross-section view, a surface of the first raised source layer is at a height that is higher than a height of a surface of the second raised source layer, and a surface of the first raised drain layer is at a height that is higher than a height of a surface of the second raised drain layer,
wherein a width of the first raised source layer in the gate width direction of the first gate electrode is less than a width of the second raised source layer in the gate width direction of the second gate electrode, and a width of the first raised drain layer in the gate width direction of the first gate electrode is less than a width of the second raised drain layer in the gate width direction of the second gate electrode,
wherein, in a plan view, an end of the first active region in a gate length direction of the first gate electrode is bounded by a first oxide layer, and an end of the second active region in a gate length direction of the second gate electrode is bounded by a second oxide layer, and
wherein, in the plan view, a width of the first oxide layer in the gate length direction of the first gate electrode is greater than a width of the second oxide layer in the gate length direction of the second gate electrode.

2. The semiconductor device according to claim 1 ,
wherein the height of the surface of the first raised source layer refers to a height at the highest position of the surface of the first raised source layer, and the height of the surface of the second raised source layer refers to a height at the highest position of the surface of the second raised source layer, and
wherein the height of the surface of the first raised drain layer refers to a height at the highest position of the surface of the first raised drain layer, and the height of the surface of the second raised drain layer refers to a height at the highest position of the surface of the second raised drain layer.

3. The semiconductor device according to claim 1 ,
wherein, in a cross-section view, a thickness of the first raised source layer is larger than a thickness of the second raised source layer, and a thickness of the first raised drain layer is larger than a thickness of the second raised drain layer.

4. The semiconductor device according to claim 1 ,
wherein the first raised source layer includes a silicide film formed on a surface layer thereof, and the second raised source layer includes a silicide film formed on a surface layer thereof, and
wherein the first raised drain layer includes a silicide film formed on a surface layer thereof, and the second raised drain layer includes a silicide film formed on a surface layer thereof.

5. The semiconductor device according to claim 1 , further comprising:
an SOI substrate including:
a support substrate;
a buried insulating layer formed on the support substrate; and
a silicon layer formed on the buried insulating layer,

wherein the first active region and the second active region are formed in the silicon layer of the SOI substrate.

6. The semiconductor device according to claim 5 ,
wherein a thickness of the first raised source layer measured based upon an upper surface of the silicon layer is made larger than a thickness of the second raised source layer measured based upon the upper surface of the silicon layer, and
wherein a thickness of the first raised drain layer measured based upon the upper surface of the silicon layer is made larger than a thickness of the second raised drain layer measured based upon the upper surface of the silicon layer.

7. The semiconductor device according to claim 5 ,
wherein a thickness of the first raised source layer measured based upon an upper surface of the buried insulating layer is made larger than a thickness of the second raised source layer measured based upon an upper surface of the buried insulating layer, and
wherein a thickness of the first raised drain layer measured based upon an upper surface of the buried insulating layer is made larger than a thickness of the second raised drain layer measured based upon the upper surface of the buried insulating layer.

8. The semiconductor device according to claim 1 ,
wherein the first field effect transistor and the second field effect transistor are components of circuits having the same function.

9. The semiconductor device according to claim 8 ,
wherein the circuits are logic circuits.

10. The semiconductor device according to claim 8 ,
wherein the circuits are SRAMs.

11. The semiconductor device according to claim 1 ,
wherein the first field effect transistor and the second field effect transistor are components of circuits having mutually different functions.

12. The semiconductor device according to claim 11 ,
wherein the first field effect transistor is a component of an SRAM, and the second field effect transistor is a component of a logic circuit.

13. The semiconductor device according to claim 1 , wherein a thickness of the first source and drain regions is substantially equal to a thickness of the second source and drain regions.

14. The semiconductor device according to claim 1 , wherein the first source and drain regions comprise a low concentration impurity diffusion region and a high concentration impurity diffusion region, and
wherein the second source and drain regions comprise a low concentration impurity diffusion region and a high concentration impurity diffusion region.

15. The semiconductor device according to claim 1 , wherein the first raised source and drain layers and the second raised source and drain layers, comprise an epitaxial silicon layer and a silicide layer formed on the epitaxial silicon layer.

16. The semiconductor device according to claim 1 , further comprising:
an interlayer insulating film formed on the first and second raised source layers and the first and second raised drain layers;
first and second contact plugs formed in the interlayer insulating film and contacting the first raised source and drain layers; an

Assignees

• Renesas Electronics Corp

Inventors

• Shinohara Hirofumi
• Oda Hidekazu
• Iwamatsu Toshiaki

Classifications

• H01L21/823418

  Electricity · mapped topic

• H01L27/1203

  Electricity · mapped topic

• H01L27/1104

  Electricity · mapped topic

• H01L27/088

  Electricity · mapped topic

• H01L21/84

  Electricity · mapped topic