Memory device having improved memory cell structures to prevent formation of voids therein

Patent metadata

Field	Value
Publication number	US-12433177-B2
Application number	US-202318106740-A
Country	US
Kind code	B2
Filing date	Feb 7, 2023
Priority date	Aug 7, 2020
Publication date	Sep 30, 2025
Grant date	Sep 30, 2025

Abstract

A memory device includes a memory cell comprising a bottom electrode, a top electrode, and a dielectric layer interposed between the bottom electrode and the top electrode. The bottom electrode has a first width W1. The top electrode has a top surface that has a second width W2 between two edges of the top surface. The memory cell has a first height H1 extending from a lower surface of the bottom electrode to the top surface of the top electrode. The memory device further includes a top contact wire coupled to the top electrode. The top contact wire has a top surface that has a third width W3, a second height H2 at a location between two adjacent memory cells, and a third height H3 extending between the top surface of the top contact wire and the insulating layer, where W1>W3>W2 and H2>H1>H3.

First claim

What is claimed is:

1. A memory device comprising:
a memory cell comprising a bottom electrode, a top electrode, and a dielectric layer interposed between the bottom electrode and the top electrode, wherein:
the bottom electrode has a first width W 1 ;
the top electrode has a top surface that has a second width W 2 between two edges of the top surface; and
the memory cell has a first height H 1 extending from a lower surface of the bottom electrode to the top surface of the top electrode;

an insulating layer covering side surfaces of the memory cell; and
a top contact wire coupled to the top electrode via an opening in the insulating layer, wherein the top contact wire has a top surface that has a third width W 3 , a second height H 2 at a location between two adjacent memory cells, and a third height H 3 extending between the top surface of the top contact wire and the insulating layer,
wherein the widths and the heights satisfy the following conditions: W 1 >W 3 >W 2 and H 2 >H 1 >H 3 .

2. The memory device of claim 1 , wherein an angle between the lower surface of the bottom electrode and one of the side surfaces of the memory cell is less than 82 degrees.

3. The memory device of claim 1 , wherein the top surface of the top electrode is flat, convex, or concave.

4. The memory device of claim 1 , wherein a distance between bottom electrodes of the two adjacent memory cells is smaller than the third width W 3 .

5. The memory device of claim 1 , wherein the dielectric layer is a resistive layer that has resistance varying depending on a voltage between the top electrode and the bottom electrode.

6. The memory device of claim 5 , wherein the resistive layer includes a first film and a second film disposed on the first film, the second film being different from the first film.

7. The memory device of claim 6 , wherein:
the first film includes a first metal oxide; and
the second film includes a second metal oxide.

8. The memory device of claim 1 , wherein the insulating layer is a first insulating layer and the memory device further comprises a second insulating layer disposed on the first insulating layer and between two adjacent top contact wires.

9. The memory device of claim 8 , wherein the second insulating layer includes no voids between the two adjacent top contact wires.

10. The memory device of claim 8 , wherein the first insulating layer includes silicon oxide.

11. The memory device of claim 10 , wherein the second insulating layer includes a low dielectric material.

12. The memory device of claim 8 , wherein the second insulating layer has a thickness greater than a thickness of the first insulating layer.

13. The memory device of claim 1 , further comprising a bottom contact wire coupled to the bottom electrode.

14. The memory device of claim 1 , wherein the bottom electrode includes at least one of TiN, TaN, or W.

15. The memory device of claim 1 , wherein the top electrode includes at least one of TiN, TaN, or Ru.

16. The memory device of claim 1 , wherein the second height H 2 is greater than the first height H 1 by at least 10 nm.

17. The memory device of claim 16 , wherein the first height H 1 is greater than the third height H 3 by at least 10 nm.

18. The memory device of claim 8 , further comprising a third insulating layer interposed between the first insulating layer and the top electrode.

19. The memory device of claim 1 , wherein a thickness of the top electrode is at least two times a thickness of the dielectric layer.

20. A memory device comprising:
a plurality of memory cells, each of the memory cells comprising a bottom electrode, a top electrode, and a dielectric layer interposed between the bottom electrode and the top electrode, wherein each of the memory cells has a first height H 1 extending from a lower surface of the bottom electrode to the top surface of the top electrode;
an insulating layer covering side surfaces of the memory cells; and
a top contact wire coupled to the top electrode via an opening in the insulating layer, wherein the top contact wire has a top surface that has a width, a second height H 2 at a location between two adjacent memory cells, and a third height H 3 extending between the top surface of the top contact wire and the insulating layer,
wherein a distance between bottom electrodes of the two adjacent memory cells is smaller than the width; and
wherein the heights satisfy the following condition: H 2 >H 1 >H 3 .

Assignees

• Hefei Reliance Memory Ltd

Inventors

• Ninomiya Takeki

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10N70/883

  Oxides or nitrides · CPC title

• H10B63/34

  of the vertical channel field-effect transistor type · CPC title

• H10N70/8833

  Binary metal oxides, e.g. TaOx · CPC title