Electrode connection structure and method of forming the same

Patent metadata

Field	Value
Publication number	US-12433144-B2
Application number	US-202217879903-A
Country	US
Kind code	B2
Filing date	Aug 3, 2022
Priority date	May 13, 2022
Publication date	Sep 30, 2025
Grant date	Sep 30, 2025

Abstract

An electrode connection structure is provided and includes a substrate, a first electrode, a second electrode, a semiconductor layer, a third electrode, and a conductive block. The first electrode and the second electrode are located on the substrate. The semiconductor layer is located on the first electrode and the second electrode. The third electrode is on the semiconductor layer. The conductive block penetrates through the semiconductor layer and the third electrode and directly contacts the second electrode and the third electrode. A first upper surface of the conductive block and a second upper surface of the third electrode are in different planes.

First claim

What is claimed is:

1. An electrode connection structure, comprising:
a substrate;
a first electrode and a second electrode located on the substrate;
a semiconductor layer located on the first electrode and the second electrode;
a third electrode located on the semiconductor layer; and
a conductive block penetrating through the semiconductor layer and the third electrode and directly contacting the second electrode and the third electrode, wherein a first upper surface of the conductive block and a second upper surface of the third electrode are in different planes.

2. The electrode connection structure of claim 1 , wherein the conductive block further comprises an extended portion covering the second upper surface of the third electrode.

3. The electrode connection structure of claim 1 , wherein the semiconductor layer comprises a photoactive layer, a carrier transport layer, or a combination thereof, and a material of the photoactive layer comprises an organic semiconductor, a quantum dot, a perovskite, or combinations thereof.

4. The electrode connection structure of claim 1 , wherein the first upper surface of the conductive block is higher than the second upper surface of the third electrode.

5. The electrode connection structure of claim 1 , wherein a material of the conductive block is the same as a material of the third electrode.

6. The electrode connection structure of claim 1 , wherein a material of the conductive block is different from a material of the third electrode.

7. The electrode connection structure of claim 1 , further comprising a package layer disposed on the third electrode, the conductive block, and an edge portion of the substrate to completely cover the third electrode, the conductive block, and the semiconductor layer.

8. A method of forming an electrode connection structure, comprising:
forming a first electrode and a second electrode on a substrate;
forming a semiconductor layer on the first electrode and the second electrode;
forming a third electrode on the semiconductor layer;
forming a through-hole penetrating through the third electrode and the semiconductor layer to expose the second electrode; and
depositing a conductive block in the through-hole, wherein the conductive block directly contacts the second electrode and the third electrode, and a first upper surface of the conductive block and a second upper surface of the third electrode are in different planes.

9. The method of claim 8 , wherein forming the through-hole penetrating through the third electrode and the semiconductor layer to expose the second electrode comprises:
forming a photoresist layer on the third electrode;
patterning the photoresist layer to form an opening exposing the third electrode;
etching the third electrode in the opening and the semiconductor layer below the third electrode to form the through-hole; and
removing the photoresist layer.

10. The method of claim 8 , wherein forming the through-hole penetrating through the third electrode and the semiconductor layer to expose the second electrode comprises:
removing a portion of the third electrode and a portion of the semiconductor layer with a laser to form the through-hole.

11. The method of claim 8 , further comprising before forming the third electrode on the semiconductor layer,
forming a mask on a portion of the semiconductor layer,
wherein forming the through-hole penetrating through the third electrode and the semiconductor layer to expose the second electrode comprises:
removing the mask, wherein the third electrode has an opening exposing the portion of the semiconductor layer;
forming a patterned photoresist layer on the third electrode, the patterned photoresist layer having an opening communicating with the opening of the third electrode;
etching or striping the portion of the semiconductor layer in the opening of the third electrode to form the through-hole; and
removing the patterned photoresist layer.

12. The method of claim 8 , further comprising before forming the third electrode on the semiconductor layer,
forming a mask on a portion of the semiconductor layer,
wherein forming the through-hole penetrating through the third electrode and the semiconductor layer to expose the second electrode comprises:
removing the mask, wherein the third electrode has an opening exposing the portion of the semiconductor layer; and
removing the portion of the semiconductor layer in the opening of the third electrode with a laser to form the through-hole.

13. The method of claim 8 , wherein depositing the conductive block in the through-hole comprises:
forming a mask on the third electrode, the mask having an opening exposing the through-hole;
depositing the conductive block in the through-hole; and
removing the mask.

14. The method of claim 8 , wherein depositing the conductive block in the through-hole comprises:
forming a photoresist layer on the third electrode and in the through-hole;
patterning the photoresist layer to form an opening exposing the through-hole;
depositing the conductive block in the through-hole; and
removing the photoresist layer.

15. The method of claim 8 , wherein the semiconductor layer comprises a photoactive layer, a carrier transport layer, or a combination thereof, and a material of the photoactive layer comprises an organic semiconductor, a quantum dot, a perovskite, or combinations thereof.

Assignees

• Raynergy Tek Inc

Inventors

• Chang Yi-Ming

Classifications

• H10H29/142

  Two-dimensional arrangements, e.g. asymmetric LED layout · CPC title

• H10K59/1201

  Manufacture or treatment · CPC title

• H10K59/131

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10K39/00

  Integrated devices, or assemblies of multiple devices, comprising at least one organic radiation-sensitive element covered by group H10K30/00 · CPC title

• H01G9/0029

  Processes of manufacture · CPC title