Display substrate and display panel with overlapping conductor layer in peripheral area

Patent metadata

Field	Value
Publication number	US-12433115-B2
Application number	US-202117628689-A
Country	US
Kind code	B2
Filing date	Feb 24, 2021
Priority date	Feb 24, 2021
Publication date	Sep 30, 2025
Grant date	Sep 30, 2025

Abstract

A display substrate and a display panel, the display substrate includes a base substrate and a plurality of sub-pixels, a plurality of data lines and a plurality of data wirings located on the base substrate. The plurality of data wirings includes a first data wiring, a second data wiring and a third data wiring that are periodically arranged. The first data wiring is located in a first conductor layer. The second data wiring is located in a second conductor layer. The third data wiring is located in a third conductor layer. An orthographic projection of a part of at least one first data wiring on the base substrate overlaps with an orthographic projection of a part of at least one third data wiring on the base substrate.

First claim

What is claimed is:

1. A display substrate, comprising:
a base substrate comprising a display area and a peripheral area surrounding the display area;
a plurality of sub-pixels in the display area;
a plurality of data lines in the display area, wherein the plurality of data lines are arranged in a first direction and extend in a second direction, and the plurality of data lines are connected to the plurality of sub-pixels;
a plurality of data wirings in the peripheral area, wherein the plurality of data wirings are located on a side of the display area in the second direction, and the plurality of data wirings are respectively connected to the plurality of data lines,
wherein the plurality of data wirings comprises a first data wiring, a second data wiring and a third data wiring that are periodically arranged, wherein the first data wiring is located in a first conductor layer, the second data wiring is located in a second conductor layer, and the third data wiring is located in a third conductor layer, wherein the first conductor layer is located on a side of the base substrate facing the plurality of sub-pixels, the second conductor layer is located on a side of the first conductor layer away from the base substrate, the third conductor layer is located on a side of the second conductor layer away from the base substrate, and an orthographic projection of a part of at least one first data wiring on the base substrate overlaps with an orthographic projection of a part of at least one third data wiring on the base substrate;
wherein a bending area is disposed in the peripheral area, the bending area is located on a side of the plurality of data wirings away from the display area in the second direction, the display substrate further comprises a plurality of patterned wirings in the bending area, and the plurality of patterned wirings are correspondingly connected to the plurality of data wirings;
wherein the display substrate further comprises a plurality of connecting wirings in the peripheral area, wherein the plurality of connecting wirings are located on a side of the bending area away from the display area in the second direction, and the plurality of connecting wirings are correspondingly connected to the plurality of patterned wirings;
wherein the plurality of connecting wirings comprise a first connecting wiring, a second connecting wiring and a third connecting wiring that are periodically arranged, wherein the first connecting wiring is located in the first conductor layer, the second connecting wiring is located in the second conductor layer, and the third connecting wiring is located in the third conductor layer;
wherein each first data wiring is connected to one third connecting wiring through one patterned wiring, each second data wiring is connected to one third connecting wiring through one patterned wiring, and each third data wiring is connected to one first connecting wiring or one second connecting wiring through one patterned wiring;
wherein, in any two adjacent third data wirings, one third data wiring is connected to the first connecting wiring through one patterned wiring, the other one third data wiring is connected to the second connecting wiring through one patterned wiring;
wherein the display substrate further comprises an auxiliary circuit in the peripheral area, wherein the auxiliary circuit is located on a side of the plurality of connecting wirings away from the display area in the second direction,
the connecting wiring further comprise a third sub-connecting-wiring, the third sub-connecting-wiring is connected to the auxiliary circuit, a second sub-connecting-wiring is connected between a first sub-connecting-wiring and the third sub-connecting-wiring;
wherein the auxiliary circuit comprises an electrostatic discharging circuit, the electrostatic discharging circuit comprises a plurality of electrostatic discharging units, the plurality of electrostatic discharging units are connected to third sub-connecting-wirings of the plurality of connecting wirings in one-to-one correspondence.

2. The display substrate of claim 1 , wherein each of the plurality of data wirings comprises a first sub-data-wiring, a second sub-data-wiring and a third sub-data-wiring, the first sub-data-wiring is connected to at least one data line of the plurality of data lines, the third sub-data-wiring is connected to at least one patterned wiring of the plurality of patterned wirings, and the second sub-data-wiring is connected between the first sub-data-wiring and the third sub-data-wiring,
wherein an orthographic projection of the second sub-data-wiring of the at least one first data wiring on the base substrate at least partially overlaps with an orthographic projection of the second sub-data-wiring of the at least one third data wiring on the base substrate.

3. The display substrate of claim 2 , wherein the plurality of data wirings are divided into a plurality of sets of data wirings, wherein third sub-data-wirings of two data wirings that belong to two adjacent sets and are adjacent to each other are separated by a first distance in the first direction, third sub-data-wirings of two data wirings that belong to the same set and are adjacent to each other are separated by a second distance in the first direction, and the second distance is smaller than the first distance.

4. The display substrate of claim 3 , wherein the plurality of sets of data wirings comprise a first set of data wirings, a second set of data wirings, a third set of data wirings, a fourth set of data wirings, a fifth set of data wirings and a sixth set of data wirings arranged in the first direction, wherein the first set of data wirings and the sixth set of data wiring are symmetrically disposed with respect to a symmetry axis of the display substrate in the second direction, the second set of data wirings and the fifth set of data wirings are symmetrically disposed with respect to the symmetry axis, and the third set of data wirings and the fourth set of data wirings are symmetrically disposed with respect to the symmetry axis.

5. The display substrate of claim 2 , wherein an orthographic projection of the second sub-data-wiring of at least one first data wiring on the base substrate completely overlaps with an orthographic projection of the second sub-data-wiring of at least one third data wiring on the base substrate, and an orthographic projection of the second sub-data-wiring of at least one second data wiring on the base substrate does not overlap with each of the orthographic projection of the second sub-data-wiring of at least one first data wiring on the base substrate and the orthographic projection of the second sub-data-wiring of at least one third data wiring on the base substrate.

6. The display substrate of claim 1 , wherein at least one of the plurality of connecting wirings comprises a first sub-connecting-wiring and a second sub-connecting-wiring, the first sub-connecting-wiring is connected to one patterned wiring of the plurality of patterned wirings, and the second sub-connecting-wiring is connected to the first sub-connecting-wiring,
wherein the first sub-connecting-wiring of at least one of the plurality of connecting wirings extends to respective patterned wiring in a polyline shape.

7. The display substrate of claim 5 , wherein the plurality of connecting wirings are divided into a plurality sets of connecting wirings, wherein first sub-connecting-wirings of two connecting wirings that belong to two adjacent sets and are adjacent to each other are separated by a third distance in the first direction, first sub-connecting-wirings of two connecting wirings that belong to the same set and are adjacent to each other are separated by a fourth distance in the first direction, a

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Yi Hong
• Li Zhengkun
• Yan Jun
• Wang Mengqi
• Li De
• Qing Haigang

Classifications

• H10D86/00

  Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates · CPC title

• G02F1/13

  based on liquid crystals, e.g. single liquid crystal display cells · CPC title

• G02F1/1333

  Constructional arrangements; {Manufacturing methods}(G02F1/135, G02F1/136 take precedence) · CPC title

• H10K59/131 Primary

  Interconnections, e.g. wiring lines or terminals · CPC title