Manufacturing method of array substrate

Patent metadata

Field	Value
Publication number	US-10600812-B2
Application number	US-201916247592-A
Country	US
Kind code	B2
Filing date	Jan 15, 2019
Priority date	Jun 19, 2018
Publication date	Mar 24, 2020
Grant date	Mar 24, 2020

Abstract

A manufacturing method of an array substrate including following steps is provided. A plurality of scan lines are formed on a substrate having a pixel region and a fan-out region. A plurality of data lines are formed. A plurality of transistors are formed and respectively electrically connected to the corresponding scan lines and data lines. A plurality of common electrodes are formed. A plurality of pixel electrodes are formed and respectively electrically connected to the corresponding transistors. A plurality of first fan-out lines, second fan-out lines, and third fan-out lines are formed in the fan-out region. Each of the third fan-out lines includes a transparent conductive layer and an auxiliary conductive layer located on and contacting the transparent conductive layer. The third fan-out lines and the common electrodes are formed by the same photomask.

First claim

What is claimed is:

1. A manufacturing method of an array substrate, comprising:
forming a plurality of scan lines on a substrate, the substrate having a pixel region and a fan-out region;
forming a plurality of data lines;
forming a plurality of transistors, wherein each of the transistors is electrically connected to the corresponding scan line and the corresponding data line;
forming a plurality of common electrodes;
forming a plurality of pixel electrodes, wherein each of the pixel electrodes is electrically connected to the corresponding transistor;
forming a plurality of first fan-out lines in the fan-out region;
forming a plurality of second fan-out lines in the fan-out region; and
forming a plurality of third fan-out lines in the fan-out region, wherein each of the third fan-out lines comprises:
a transparent conductive layer; and
an auxiliary conductive layer, disposed on the transparent conductive layer and in contact with the transparent conductive layer;

wherein the third fan-out lines and the common electrodes are formed by a same photomask.

2. The manufacturing method of the array substrate according to claim 1 , wherein the step of forming the third fan-out lines and the common electrodes comprises:
forming a transparent conductive material layer, an auxiliary conductive material layer and a photoresist material layer in sequence;
patterning the photoresist material layer by using a photomask, thereby forming a photoresist layer, wherein the photoresist layer comprises:
a plurality of first blocks disposed in the pixel region; and
a plurality of second blocks disposed in the fan-out region, a thickness of each of the second blocks smaller than a thickness of each of the first blocks;

patterning the auxiliary conductive material layer by using the photoresist layer to form the auxiliary conductive layers in the fan-out region and a remaining auxiliary conductive material layer in the pixel region, wherein a portion of each of the auxiliary conductive layers is overlapped with both of the corresponding first fan-out line and the corresponding second fan-out line;
patterning the transparent conductive material layer by using the photoresist layer to form the transparent conductive layer in the fan-out region and the common electrodes in the pixel region;
removing the first blocks;
removing the remaining auxiliary conductive material layer; and
removing the second blocks.

3. The manufacturing method of the array substrate according to claim 1 , wherein each of the transistors comprises a gate, a semiconductor layer, a source and a drain, wherein the gates, the scan lines and the first fan-out lines are formed by a same metal layer.

4. The manufacturing method of the array substrate according to claim 3 , wherein the sources, the drains, the data lines and the second fan-out lines are formed by another same metal layer.

5. The manufacturing method of the array substrate according to claim 4 , further comprising forming a plurality of touch signal lines to be respectively electrically connected to the corresponding common electrodes, wherein the touch signal lines, the sources, the drains, the data lines and the second fan-out lines are formed by the another same metal layer.

6. The manufacturing method of the array substrate according to claim 1 , wherein the common electrodes and the transparent conductive layer are formed by a same conductive layer.

7. The manufacturing method of the array substrate according to claim 1 , further comprising forming a plurality of first pads, a plurality of second pads and a plurality of third pads in the fan-out region, wherein each of the first pads is electrically connected to the corresponding first fan-out line, each of the second pads is electrically connected to the corresponding second fan-out line, and each of the third pads is electrically connected to the corresponding third fan-out line.

8. The manufacturing method of the array substrate according to claim 1 , wherein each of the first fan-out lines, the second fan-out lines and the third fan-out lines has an extending portion, an extending direction of each of the extending portions is not parallel with an extending direction of each of the data lines, and portions of the extending portions of the first fan-out line, the second fan-out line and the third fan-out line adjacent to each other and arranged in sequence are completely overlapped with each other.

9. The manufacturing method of the array substrate according to claim 1 , wherein each of the first fan-out lines, the second fan-out lines and the third fan-out lines has an extending portion, an extending direction of each of the extending portions is not parallel with an extending direction of each of the data lines, and the extending portions of the first fan-out line, the second fan-out line and the third fan-out line adjacent to each other and arranged in sequence are alternately overlapped with each other.

10. A manufacturing method of an array substrate, comprising:
forming a first metal layer on a substrate having a pixel region and a fan-out region, wherein the first metal layer comprises a plurality of gates and a plurality of scan lines disposed in the pixel region and a plurality of first fan-out lines disposed in the fan-out region;
forming a gate insulating layer on the first metal layer;
forming a second metal layer on the gate insulating layer, the second metal layer comprising a plurality of sources, a plurality of drains and a plurality of data lines disposed in the pixel region and a plurality of second fan-out lines disposed in the fan-out region;
forming a first insulating layer on the second metal layer; and
forming a first conductive layer and a third metal layer on the first insulating layer by using a photomask, wherein the first conductive layer comprises a plurality of transparent conductive layers disposed in the fan-out region and a plurality of common electrodes disposed in the pixel region, the third metal layer comprises a plurality of auxiliary conductive layers disposed in the fan-out region, the auxiliary conductive layers are respectively disposed on the transparent conductive layers to constitute a plurality of third fan-out lines in the fan-out region.

11. The manufacturing method of the array substrate according to claim 10 , wherein after the step of forming the first conductive layer and the third metal layer, the method further comprises:
forming a second insulating layer on the first conductive layer and the third metal layer; and
forming a second conductive layer on the second insulating layer, wherein the second conductive layer comprises:
a plurality of pixel electrodes disposed in the pixel region and respectively electrically connected to the drains; and
a plurality of bridge electrodes disposed in the fan-out region.

12. The manufacturing method of the array substrate according to claim 10 , wherein the step of forming the first conductive layer and the third metal layer comprises:
forming a transparent conductive material layer, an auxiliary conductive material layer and a photoresist material layer on the first insulating layer in sequence;
patterning the photoresist material layer by using a photomask to form a photoresist layer, wherein the photoresist layer comprises:
a plurality of first blocks disposed in the pixel region; and
a plurality of second blocks disposed in the fan-out region, a thickness of each of the second blocks being greater than a thickness of each of the first blocks;

patterning the auxiliary conductive material layer by using the photoresist layer to form the auxiliary conductive layers in the fan-out

Assignees

• Au Optronics Corp

Inventors

• Hsu Wen-Yi
• Chen Pei-Ming
• Chen Maw-Song

Classifications

• G02F1/136286

  Wiring, e.g. gate line, drain line · CPC title

• G02F1/13452 Primary

  Conductors connecting driver circuitry and terminals of panels · CPC title

• G02F1/134363

  for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS] · CPC title

• G02F1/13338

  Input devices, e.g. touch panels · CPC title

• G02F1/1362

  Active matrix addressed cells {(G02F1/134336, G02F1/134363 take precedence)} · CPC title