Display substrate and display device

Patent metadata

Field	Value
Publication number	US-10983618-B2
Application number	US-201816303310-A
Country	US
Kind code	B2
Filing date	Apr 18, 2018
Priority date	Apr 21, 2017
Publication date	Apr 20, 2021
Grant date	Apr 20, 2021

Abstract

The embodiment of the disclosure provides a display substrate and a display device. The display substrate includes data signal lines located in a display area of the display substrate, and fanout lines in a fanout area adjacent the display area of the display substrate and respectively connected in one-to-one correspondence with the data signal lines, wherein the data signal fanout lines include first fanout lines disposed in the same layer with a touch electrode of the display substrate.

First claim

What is claimed is:

1. A display substrate comprising:
data signal lines located in a display area of the display substrate; and
data signal fanout lines in a fanout area adjacent the display area of the display substrate and respectively connected in one-to-one correspondence with the data signal lines, wherein the data signal fanout lines comprise first fanout lines disposed in the same layer with a touch electrode of the display substrate,
wherein the data signal fanout lines further comprise second fanout lines and third fanout lines, the second fanout lines being disposed in the same layer as a source/drain electrode of the display substrate, and wherein the third fanout lines are disposed in the same layer with a gate electrode of the display substrate.

2. The display substrate according to claim 1 , further comprising:
a first insulating layer between a source/drain electrode and the touch electrode;
a second insulating layer covering the touch electrode and the first insulating layer;
a first hole penetrating the first insulating layer and the second insulating layer; and
a second hole disposed in the second insulating layer, wherein at least one first fanout line is connected to the data signal lines through the first hole and the second hole.

3. The display substrate according to claim 2 , further comprising:
a third hole penetrating the first insulating layer and the second insulating layer; and
a fourth hole disposed in the second insulating layer, wherein at least one first fanout line is connected to a first bonding line through the third hole and the fourth hole.

4. The display substrate according to claim 3 , further comprising:
a third insulating layer between the source/drain electrode and the gate electrode;
a fifth hole penetrating through the first insulating layer, the second insulating layer, and the third insulating layer; and
a sixth hole disposed in the second insulating layer, wherein at least one first fanout line is connected to a second bonding line through the fifth hole and the sixth hole.

5. The display substrate according to claim 4 , further comprising:
touch signal lines disposed in the display area and in the same layer as the touch electrode; and
touch signal fanout lines located in the fanout area and respectively connected in one-to-one correspondence to the touch signal lines.

6. The display substrate according to claim 5 , wherein the data signal fanout lines and the touch signal fanout lines are spaced apart from each other.

7. The display substrate according to claim 6 , wherein an angle at which at least one first fanout line is inclined with respect to an extending direction of the data signal lines is greater than a preset value, such that an interval between the data signal fanout lines and an adjacent line is greater than an aperture of the holes in the second insulating layer.

8. The display substrate according to claim 5 , wherein the touch signal lines comprise a dummy touch signal line, and wherein the first fanout line comprises a dummy touch signal fanout line corresponding to the dummy touch signal line.

9. A display device comprising the display substrate according to claim 2 .

10. A display device comprising the display substrate according to claim 1 .

11. A display substrate comprising:
data signal lines located in a display area of the display substrate; and
data signal fanout lines in a fanout area adjacent the display area of the display substrate and respectively connected in one-to-one correspondence with the data signal lines, wherein the data signal fanout lines comprise first fanout lines disposed in the same layer with a touch electrode of the display substrate, second fanout lines, and third fanout lines, the second fanout lines being disposed in the same layer as a source/drain electrode of the display substrate, the third fanout lines being disposed in the same layer with a gate electrode of the display substrate, wherein the display substrate further comprises bonding lines in a bonding area, wherein the bonding area is located on a side of the fanout area far away from the display area, and wherein the bonding lines are connected in one-to-one correspondence with the data signal fanout lines.

12. The display substrate according to claim 11 , wherein the bonding lines comprise first bonding lines disposed in the same layer as the source/drain electrode and second bonding lines disposed in the same layer as the gate electrode, and wherein the first fanout lines are connected to at least one of the first bonding lines and the second bonding lines.

13. The display substrate according to claim 12 , wherein the second fanout lines are connected to the first bonding lines, and the third fanout lines are connected to the second bond lines.

14. A display device comprising the display substrate according to claim 13 .

15. The display substrate according to claim 12 , wherein a number of the first fanout lines connected to the first bond lines is equal to a number of the first fanout lines connected to the second bond lines.

16. A display device comprising the display substrate according to claim 15 .

17. A display device comprising the display substrate according to claim 12 .

18. A display device comprising the display substrate according to claim 11 .

Assignees

• Beijing Boe Optoelectronics Tech Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Shang Jianxing

Classifications

• H10D86/443

  adapted for preventing breakage, peeling or short circuiting · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• G02F1/136286

  Wiring, e.g. gate line, drain line · CPC title

• G06F3/04164

  Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads · CPC title