Semiconductor device including self-aligned contact and method of manufacturing the semiconductor device

Patent metadata

Field	Value
Publication number	US-12433015-B2
Application number	US-202218050219-A
Country	US
Kind code	B2
Filing date	Oct 27, 2022
Priority date	Jan 10, 2020
Publication date	Sep 30, 2025
Grant date	Sep 30, 2025

Abstract

A semiconductor device according to some embodiments of the disclosure may include a fin type active pattern extending in a first direction, a plurality of gate structures on the fin type active pattern and extending in a second direction different from the first direction, a plurality of inter-contact insulation patterns on respective ones of the plurality of gate structures, a plurality of interlayer insulation layers on side surfaces of the plurality of gate structures, and a plurality of contact plugs respectively between pairs of the plurality of gate structures. The fin type active pattern may include a plurality of source/drains. Lower ends of the plurality of contact plugs may contact the plurality of source/drains. The plurality of gate structures may each include a first gate metal, a second gate metal, a gate capping layer, a gate insulation layer, a first spacer, and a second spacer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a fin type active pattern extending in a first direction;
a plurality of gate structures on the fin type active pattern and extending in a second direction different from the first direction;
a plurality of inter-contact insulation patterns on respective ones of the plurality of gate structures;
a plurality of interlayer insulation layers on side surfaces of the plurality of gate structures; and
a plurality of contact plugs respectively between pairs of the plurality of gate structures,
wherein the fin type active pattern comprises a plurality of source/drains,
wherein lower ends of the plurality of contact plugs contact respective ones of the plurality of source/drains,
wherein the plurality of gate structures each comprises:
a first gate metal;
a second gate metal on a side surface and a lower portion of the first gate metal;
a gate capping layer on the first gate metal and the second gate metal;
a gate insulation layer on a side surface and a lower portion of the second gate metal and a lower portion of a side surface of the gate capping layer;
a first spacer on a side surface of the gate insulation layer and the side surface of the gate capping layer;
a second spacer on a side surface of the first spacer; and
a plurality of gate layers sequentially stacked apart from one another on a lower portion of the gate insulation layer,
wherein an upper surface of the second spacer is asymmetrical with respect to a center axis extending in a vertical direction perpendicular to the first and second directions of the inter-contact insulation patterns,
wherein the gate capping layer is free from overlap by the plurality of contact plugs in the vertical direction,
wherein an uppermost surface of the gate capping layer is concavely recessed,
wherein each of the plurality of inter-contact insulation patterns is disposed on the gate capping layer, the first spacer, and the second spacer, and
wherein a bottom surface of each of the plurality of inter-contact insulation patterns protrudes downward toward the first gate metal and the second gate metal.

2. The semiconductor device of claim 1 , wherein the second spacer comprises an internal second spacer and an external second spacer,
wherein the internal second spacer and the external second spacer include a low-k material, and
wherein the interlayer insulation layers are spaced apart from the inter-contact insulation patterns.

3. The semiconductor device of claim 1 , wherein the fin type active pattern further comprises a silicide layer between ones of the plurality of contact plugs and between ones of the plurality of source/drains, and
wherein an uppermost surface of the gate insulation layer is at a level that is higher than an uppermost surface of the second gate metal, with respect to the fin type active pattern.

4. The semiconductor device of claim 1 , wherein the gate capping layer comprises an outer side surface that is inclined so that an area of a horizontal cross-sectional surface thereof increases toward an upper portion thereof in a direction away from the fin type active pattern.

5. The semiconductor device of claim 1 , wherein the uppermost surface of the gate capping layer, an uppermost surface of the first spacer, and an uppermost surface of the second spacer are at a level that is higher than a lowermost surface of each of the plurality of inter-contact insulation patterns, with respect to the fin type active pattern, and
wherein the uppermost surface of the gate capping layer has a round shape.

6. The semiconductor device of claim 1 , wherein a top surface of the first spacer is downward recessed towards the fin type active pattern, and
wherein a top surface of at least one of the plurality of inter-contact insulation patterns is at least partially rounded.

7. A semiconductor device comprising:
a fin type active pattern that extends in a first direction;
a plurality of gate structures on the fin type active pattern and extending in a second direction different from the first direction;
a plurality of inter-contact insulation patterns on respective ones of the plurality of gate structures;
a plurality of interlayer insulation layers on side surfaces of the plurality of gate structures; and
a plurality of contact plugs respectively between pairs of the plurality of gate structures,
wherein the fin type active pattern comprises a plurality of source/drains,
wherein lower ends of the plurality of contact plugs contact respective ones of the plurality of source/drains,
wherein the plurality of gate structures each comprises:
a first gate metal;
a second gate metal on a side surface and a lower portion of the first gate metal;
a gate capping layer on the first gate metal and the second gate metal;
a gate insulation layer on a side surface and a lower portion of the second gate metal and a lower portion of a side surface of the gate capping layer;
a first spacer on a side surface of the gate insulation layer and the gate capping layer; and
a second spacer on a side surface of the first spacer,
wherein an uppermost surface of the second spacer is asymmetrical with respect to a center axis of the inter-contact insulation patterns, such that a side surface of a respective one of the inter-contact insulation patterns is substantially aligned with a side surface of the respective second spacer in a vertical direction perpendicular to the first and second directions, and
wherein an uppermost surface of the gate capping layer has a round shape that is concavely recessed.

8. The semiconductor device of claim 7 ,
wherein a top surface of the first spacer is downward recessed towards the fin type active pattern, and
wherein the side surface of the gate capping layer is inclined so that a width of the gate capping layer in the first direction increases toward an upper portion of the gate capping layer in a direction away from the fin type active pattern.

9. The semiconductor device of claim 7 , wherein the second spacer comprises an internal second spacer and an external second spacer, and
wherein a top surface of the internal second spacer is downward recessed towards the fin type active pattern.

10. The semiconductor device of claim 7 , wherein the uppermost surface of the gate capping layer, an uppermost surface of the first spacer, and the uppermost surface of the second spacer are at a level that is higher than a lowermost surface of each of the plurality of inter-contact insulation patterns, with respect to the fin type active pattern.

11. The semiconductor device of claim 7 , wherein at least one of the plurality of inter-contact insulation patterns comprises a seam.

12. The semiconductor device of claim 11 , wherein two or more of the plurality of inter-contact insulation patterns each comprise a respective seam such that there is a plurality of respective seams, and at least one of the plurality of respective seams extends vertically along a center axis of a respective one of the plurality of inter-contact insulation patterns, and
wherein the at least one of the plurality of respective seams and a center of the respective gate capping layer are misaligned with each other in the vertical direction.

13. The semiconductor device of claim 7 , wherein top surfaces of the plurality of inter-contact insulation patterns and top surfaces of the plurality of contact plugs are coplanar.

14. The semiconductor device of claim 7 , wherein each of the plurality of inter-contact insulation patterns and a center of the gate capping layer are misaligned with each other.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Sanghyun
• Kang Sungwoo
• Park Jongchul
• Oh Youngmook
• Lee Jeongyun

Classifications

• H10W20/0696

  by using sacrificial placeholders, e.g. using sacrificial plugs · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/071

  of dielectric parts thereof · CPC title

• H10D30/6219

  characterised by the source or drain electrodes · CPC title

• H10D30/6211

  having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates · CPC title