Semiconductor devices utilizing capping layers with multiple widths and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10043879-B1
Application number	US-201715660432-A
Country	US
Kind code	B1
Filing date	Jul 26, 2017
Priority date	Mar 9, 2017
Publication date	Aug 7, 2018
Grant date	Aug 7, 2018

Abstract

A semiconductor device includes a fin active region protruding from a substrate and extending in a first direction, a gate electrode covering an upper surface and sidewalls of the fin active region and extending in a second direction crossing the first direction, a gate spacer structure on opposite sidewalls of the gate electrode, an insulating capping layer on the gate electrode and extending in the second direction, an insulating liner on opposite sidewalls of the gate electrode and on an upper surface of the gate spacer structure, and a self-aligned contact at a side of the gate electrode. The insulating liner may have a second thickness greater than a first thickness of the gate spacer structure. A sidewall of the self-aligned contact may be in contact with the gate spacer structure and the insulating liner.

First claim

What is claimed is:

1. A semiconductor device comprising:
a fin active region protruding from a substrate, the fin active region extending in a first direction parallel to an upper surface of the substrate;
a gate electrode on an upper surface and sidewalls of the fin active region, the gate electrode extending in a second direction across the fin active region;
a gate spacer structure on a sidewall of the gate electrode, an upper surface of the gate spacer structure positioned at a higher level than an upper surface of the gate electrode relative to the upper surface of the substrate;
an insulating capping layer on the gate electrode, a first portion of the insulating capping layer having a first width greater than a second width of the gate electrode in the first direction;
an insulating liner on a sidewall of the insulating capping layer and on the upper surface of the gate spacer structure, the insulating liner having a second thickness less than a first thickness of the gate spacer structure in the first direction;
a source/drain region at a side of the gate electrode;
a self-aligned contact connected to the source/drain region, a sidewall of the self-aligned contact being in contact with the gate spacer structure and the insulating liner; and
a native oxide layer between the insulating liner and the insulating capping layer.

2. The semiconductor device of claim 1 , wherein the native oxide layer extends from between the insulating liner and the insulating capping layer to between the gate spacer structure and the insulating capping layer.

3. The semiconductor device of claim 1 , wherein the second thickness of the insulating liner is greater than a third thickness of the native oxide layer, and
wherein the insulating liner includes nitride.

4. The semiconductor device of claim 1 , wherein the first portion of the insulating capping layer is positioned at a higher level than the upper surface of the gate spacer structure relative to the upper surface of the substrate,
wherein a second portion of the insulating capping layer is positioned at a lower level than the upper surface of the gate spacer structure relative to the upper surface of the substrate, and
wherein a third width of the second portion of the insulating capping layer is less than the first width of the first portion of the insulating capping layer in the first direction.

5. The semiconductor device of claim 1 , wherein the gate spacer structure includes a first spacer layer on the sidewall of the gate electrode, a second spacer layer on the first spacer layer and a third spacer layer on the second spacer layer,
wherein the second spacer layer includes an insulating material having a lower dielectric constant than that of the first and second spacer layers, and
wherein the self-aligned contact is not in contact with the second spacer layer.

6. The semiconductor device of claim 1 , wherein a lower surface of the insulating liner contacts the upper surface of the gate spacer structure and is positioned at a higher level than the upper surface of the gate electrode relative to the upper surface of the substrate.

7. The semiconductor device of claim 1 , wherein the substrate includes a line cut region that is spaced apart from the fin active region, and
wherein the gate spacer structure and the insulating liner extend to the line cut region.

8. The semiconductor device of claim 7 , further comprising a line gap-fill insulating layer on the substrate in the line cut region,
wherein the gate spacer structure and the insulating liner are on a sidewall of the line gap-fill insulating layer.

9. The semiconductor device of claim 8 , wherein an upper surface of the gate spacer structure on the sidewall of the line gap-fill insulating layer is positioned at substantially the same level as the upper surface of the gate spacer structure on the sidewall of the gate electrode relative to the upper surface of the substrate.

10. A semiconductor device comprising:
a fin active region protruding from a substrate, the fin active region extending in a first direction parallel to an upper surface of the substrate;
a gate electrode covering an upper surface and sidewalls of the fin active region, the gate electrode extending in a second direction crossing the first direction;
a gate spacer structure on opposite sidewalls of the gate electrode;
an insulating capping layer on the gate electrode, the insulating capping layer extending in the second direction;
an insulating liner on opposite sidewalls of the insulating capping layer and on an upper surface of the gate spacer structure, the insulating liner extending in the second direction and having a second thickness smaller than a first thickness of the gate spacer structure;
a native oxide layer between the insulating liner and the insulating capping layer; and
a self-aligned contact at a side of the gate electrode, a sidewall of the self-aligned contact being in contact with the gate spacer structure and the insulating liner.

11. The semiconductor device of claim 10 , wherein the upper surface of the gate spacer structure is positioned at a higher level than an upper surface of the gate electrode relative to the upper surface of the substrate.

12. The semiconductor device of claim 10 , wherein the upper surface of the gate spacer structure is sloped toward the gate electrode.

13. The semiconductor device of claim 10 , wherein a first width of an upper portion of the insulating capping layer is greater than a second width of a lower portion of the insulating capping layer, and
wherein the insulating capping layer has a T-shape.

14. The semiconductor device of claim 10 , wherein the sidewall of the self-aligned contact is in contact with the insulating capping layer.

15. A semiconductor device comprising:
a substrate;
a fin active region protruding from the substrate, the fin active region extending in a first direction;
a gate electrode on the fin active region, the gate electrode extending in a second direction that crosses the first direction;
a gate spacer structure on a sidewall of the gate electrode;
an insulating capping layer on the gate electrode, the insulating capping layer comprising a first upper portion having a first width and a second lower portion having a second width, smaller than the first width, between the first upper portion and the substrate; and
an insulating liner on an upper surface of the gate spacer structure and on a sidewall of the insulating capping layer, the insulating liner comprising a second thickness in the first direction that is smaller than a first thickness of the gate spacer structure in the first direction,
wherein the insulating liner does not extend between the gate electrode and the insulating capping layer that is on the gate electrode.

16. The semiconductor device of claim 15 , wherein the gate spacer structure comprises a first spacer layer, a second spacer layer on the first spacer layer, and a third spacer layer on the second spacer layer, and
wherein the second spacer layer comprises a material having a dielectric constant lower than that of the first spacer layer and the third spacer layer.

17. The semiconductor device of claim 16 , further comprising a source/drain region adjacent the gate electrode, and
a contact adjacent the gate electrode and coupled to the source/drain region,
wherein an upper portion of the contact contacts the insulating capping layer,
wherein a lower portion of the contact contacts the third spacer layer of the gate spacer structure, and
wherein the contact

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Yoon-Jae
• Kim Ho-Young
• Kim Dong-Kwon
• Yoo Jin-Hyuk
• Jung Woo-Jin

Classifications

• H10D30/6219

  characterised by the source or drain electrodes · CPC title

• H10D30/024 Primary

  of fin field-effect transistors [FinFET] · CPC title

• H10D64/20 Primary

  Electrodes characterised by their shapes, relative sizes or dispositions · CPC title

• H01L29/518

  Electricity · mapped topic

• H01L29/785

  Electricity · mapped topic