Method for forming a two-layered hard mask on top of a gate structure
US-2016315007-A1 · Oct 27, 2016 · US
Method for fabricating semiconductor device
US9941161B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9941161-B2 |
| Application number | US-201514838374-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 28, 2015 |
| Priority date | Aug 3, 2015 |
| Publication date | Apr 10, 2018 |
| Grant date | Apr 10, 2018 |
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- Title
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Abstract
Official abstract text for this publication.
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon, a first hard mask atop the gate structure, and an interlayer dielectric (ILD) layer around the gate structure and the first hard mask; removing part of the first hard mask; forming a second hard mask layer on the first hard mask and the ILD layer; and planarizing part of the second hard mask layer to form a second hard mask on the first hard mask.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for fabricating semiconductor device, comprising: providing a substrate having a gate structure thereon, a first hard mask atop the gate structure, and an interlayer dielectric (ILD) layer around the gate structure and the first hard mask; removing part of the first hard mask; forming a second hard mask layer on the first hard mask and the ILD layer; and planarizing part of the second hard mask layer and part of the ILD layer at the same time to form a second hard mask on the first hard mask. 2. The method of claim 1 , wherein the width of the second hard mask is greater than the width of the first hard mask. 3. The method of claim 1 , wherein a spacer and a contact etch stop layer (CESL) are formed adjacent to the gate structure and the first hard mask, the method further comprises: removing part of the first hard mask and part of the spacer; and forming the second hard mask on the first hard mask and the spacer. 4. The method of claim 1 , wherein a spacer and a contact etch stop layer (CESL) are formed adjacent to the gate structure and the first hard mask, the method further comprises: removing part of the first hard mask, part of the spacer, and part of the CESL; and forming the second hard mask on the first hard mask, the spacer, and the CESL. 5. The method of claim 1 , wherein the first hard mask and the second hard mask comprise different material. 6. The method of claim 1 , wherein the second hard mask comprises TiN. 7. The method of claim 1 , further comprising forming a cap layer on the first hard mask and the ILD layer before forming the second hard mask layer. 8. The method of claim 7 , wherein the cap layer comprises an oxide layer. 9. The method of claim 1 , further comprising removing part of the ILD layer after forming the second hard mask. 10. The method of claim 1 , further comprising using the second hard mask to form a contact hole adjacent to the gate structure after planarizing part of the second hard mask layer. 11. A method for fabricating semiconductor device, comprising: providing a substrate having a gate structure thereon, a spacer around the gate structure, a contact etch stop layer (CESL) adjacent to the spacer, a first hard mask atop the gate structure, and an interlayer dielectric (ILD) layer around the gate structure and the first hard mask; removing part of the first hard mask and part of the spacer simultaneously so that a top surface of the first hard mask and the spacer is lower than a top surface of the CESL; forming a second hard mask layer on the first hard mask and the ILD layer; and planarizing part of the second hard mask layer to form a second hard mask on the first hard mask. 12. The method of claim 11 , wherein the top surfaces of the second hard mask and the CESL are coplanar.
Assignees
Inventors
Classifications
Planarisation of inorganic insulating materials · CPC title
of semiconductor materials · CPC title
of conductive or resistive materials · CPC title
of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers · CPC title
- H10W20/069Primary
by forming self-aligned vias or self-aligned contact plugs · CPC title
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- What does patent US9941161B2 cover?
- A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon, a first hard mask atop the gate structure, and an interlayer dielectric (ILD) layer around the gate structure and the first hard mask; removing part of the first hard mask; forming a second hard mask layer on the first hard mask and the ILD layer; …
- Who is the assignee on this patent?
- United Microelectronics Corp
- What technology area does this patent fall under?
- Primary CPC classification H10W20/069. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Apr 10 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 7 related publications on this page (citations in our corpus or others sharing the same primary CPC).