Technologies for interconnect address remapper with event recognition and register management

Patent metadata

Field	Value
Publication number	US-12430132-B2
Application number	US-202218282728-A
Country	US
Kind code	B2
Filing date	Mar 28, 2022
Priority date	Mar 29, 2021
Publication date	Sep 30, 2025
Grant date	Sep 30, 2025

Abstract

Systems and methods are disclosed for a configurable interconnect address remapper with event detection. For example, an integrated circuit can include a processor core configured to execute instructions. The processor core includes region registers defined by a From Address range and a To Address, a register storing a number of regions defined in the integrated circuit, interrupt enable registers associated with each pair of region registers, and event flags associated with each pair of region registers; an interconnection system handling transactions from the processor core; an interconnect address remapper translating an address associated with a transaction using the one or more pair of region registers; and an interrupt controller receiving an interrupt signal from the interconnect address remapper when the interrupt enable registers are enabled and at least one raised event flags when at least one of the one or more pair of region registers matches the transaction address.

First claim

What is claimed is:

1. An integrated circuit for executing instructions comprising:
a processor core configured to execute instructions, wherein the processor core includes:
one or more pair of region registers configured to define a From Address range and a To Address;
a region register configured to store a number of regions defined in the integrated circuit, wherein a region in defined by a pair of region registers;
interrupt enable registers dynamically interacting with each of the one or more pair of region registers; and
event flags associated with each of the one or more pair of region registers, configured to indicate a matching condition for address ranges;
an interconnection system configured to handle transactions from the processor core related to the execution of the instructions;
an interconnect address remapper configured to translate an address associated with a transaction using the one or more pair of region registers; and
an interrupt controller configured to receive an interrupt signal from the interconnect address remapper when the interrupt enable registers are enabled and at least one of the event flags is raised when at least one of the one or more pair of region registers matches the address associated with the transaction.

2. The integrated circuit of claim 1 , wherein the processor core further includes:
a flush register configured to flush valid registers associated with each of the one or more pair of region registers.

3. The integrated circuit of claim 1 , wherein for each of the one or more pair of region registers, a size of a region is an integral multiple of integer register width when there are no cache line accesses passed through the interconnect address remapper and is an integral multiple of cache line size when there are cache line accesses passed through the interconnect address remapper.

4. The integrated circuit of claim 1 , wherein From Address ranges are cached in caches local to the processor core.

5. The integrated circuit of claim 1 , wherein remapping by the interconnect address remapper occurs during a cache refill.

6. The integrated circuit of claim 1 , wherein multiple raised event flags are logically OR-ed to-together to generate the interrupt signal.

7. The integrated circuit of claim 1 , wherein each event flag includes a read event flag and a write event flag and each interrupt enable register includes a read interrupt enable register and a write interrupt enable register.

8. The integrated circuit of claim 1 , wherein a matching atomic memory operation transaction sets a read event flag and a write event flag.

9. The integrated circuit of claim 1 , wherein a To Address is set to the From Address range to monitor interconnect address remapper events to disable a translation feature.

10. The integrated circuit of claim 1 , wherein a To Address is set to an illegal value to generate an interrupt signal and halt execution proximate to matching transaction.

11. The integrated circuit of claim 1 , further comprising:
a monitor interface configured to provide signals for system level monitoring of the interconnect address remapper when the interrupt enable registers are enabled, wherein the signals include a match signal and a matching region identification signal.

12. A method comprising:
receiving a transaction associated with a memory operation at an interconnect address remapper from a processor core via an interconnect network;
translating an address associated with the transaction when the address matches a translation region, each translation region defined by a From Address range and a To Address;
raising an event flag indicating a matching condition for the translation region for a match when interrupt signaling is enabled; and
generating an interrupt signal from an interrupt controller based on the raised event flag.

13. The method of claim 12 , further comprising:
flushing a valid register associated with each region upon a reset of the interconnect address remapper.

14. The method of claim 12 , wherein for each region, a size of the region is an integral multiple of integer register width when there are no cache line accesses passed through the interconnect address remapper and is an integral multiple of cache line size when there are cache line accesses passed through the interconnect address remapper.

15. The method of claim 12 , wherein From Address ranges are cached in caches local to the processor core.

16. The method of claim 12 , wherein the translating by the interconnect address remapper occurs during a cache refill.

17. The method of claim 12 , further comprising:
logically OR-ing multiple raised event flags to generate the interrupt signal.

18. The method of claim 12 , wherein each event flag includes a read event flag and a write event flag and each interrupt enable register includes a read interrupt enable register and a write interrupt enable register.

19. The method of claim 12 , wherein a To Address is set to the From Address range to monitor interconnect address remapper events absent translation and wherein a To Address is set to an illegal value to generate an interrupt signal and halt execution proximate to matching transaction.

20. The method of claim 18 , further comprising:
raising the read event flag and the write event flag for an atomic memory operation transaction which matches a region; and
providing a match signal and a matching region identification signal for system level monitoring of the interconnect address remapper when the interrupt enable registers are enabled.

Assignees

• Sifive Inc

Inventors

• Parry David
• Barbier Drew
• Smith Josh
• Solomatnikov Alexandre
• Asanovic Krste

Classifications

• G06F13/32

  using combination of interrupt and burst mode transfer · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F9/327 Primary

  for interrupts · CPC title

• G06F13/404 Primary

  with address mapping · CPC title