Atomic layer-based surface treatments for infrared detectors

Patent metadata

Field	Value
Publication number	US-12426387-B2
Application number	US-202218049424-A
Country	US
Kind code	B2
Filing date	Oct 25, 2022
Priority date	Oct 25, 2021
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

Disclosed herein is a method of producing an infrared detector. In certain embodiments, the method includes: forming a planar multi-layer structure including an absorber including a superlattice structure; patterning the planar multi-layer structure; etching the planar multi-layer structure to define a plurality of pixels, the sidewalls of the plurality of pixels includes a sidewall roughness and multiple types of surface oxides; and performing a surface treatment process to the plurality of pixels in order to reduce the sidewall roughness and replace the surface oxides with a chlorinated surface morphology. The surface treatment process may reduce surface current of the infrared detector which may decrease the dark current in the infrared detector.

First claim

What is claimed is:

1. A method of producing an infrared detector, the method comprising:
forming a planar multi-layer structure comprising an absorber including a superlattice structure;
patterning the planar multi-layer structure;
etching the planar multi-layer structure to define a plurality of pixels, wherein sidewalls of the plurality of pixels include multiple types of surface oxides; and
performing a surface treatment process to the plurality of pixels in order to replace the surface oxides with a chlorinated surface morphology; wherein the surface treatment process comprises a first atomic layer etching process followed by a second atomic layer deposition process.

2. The method of claim 1 , wherein the planar multi-layer structure further comprises a unipolar barrier layer and a contact layer.

3. The method of claim 2 , wherein the contact layer comprises a superlattice structure.

4. The method of claim 3 , wherein the superlattice structure of the contact layer comprises a compound semiconductor.

5. The method of claim 4 , wherein the compound semiconductor comprises InAs and InAsSb.

6. The method of claim 5 , wherein the multiple types of surface oxides include indium oxide, arsenic oxide, and antimony oxide.

7. The method of claim 1 , wherein the superlattice structure of the absorber comprises a compound semiconductor.

8. The method of claim 7 , wherein the compound semiconductor comprises InAs and InAsSb.

9. The method of claim 8 , wherein the multiple types of surface oxides include indium oxide, arsenic oxide, and antimony oxide.

10. The method of claim 1 , wherein the first atomic layer etching process comprises cyclically and alternately:
exposing the sidewalls of the plurality of pixels to a fluorocarbon reactant; and
exposing the sidewalls of the plurality of pixels to an ionized argon gas.

11. The method of claim 10 , wherein the fluorocarbon reactant is CHF 3 gas.

12. The method of claim 10 , wherein exposing the sidewalls of the plurality of pixels to the fluorocarbon reactant is between 20-80 seconds.

13. The method of claim 10 , wherein exposing the sidewalls to the fluorocarbon reactant is performed with substantially no bias.

14. The method of claim 10 , exposing the sidewalls to the ionized argon gas includes exposing the sidewalls to argon gas with a bias.

15. The method of claim 14 , wherein the bias applied to the ionized argon gas is higher than a bias applied when exposing the sidewalls to the fluorocarbon reactant.

16. The method of claim 1 , wherein the second atomic layer deposition process comprises cyclically and alternately:
exposing the sidewalls of the plurality of pixels to a chlorine reactant; and
exposing the sidewalls of the plurality of pixels to an ionized argon gas.

17. The method of claim 16 , wherein the chlorine reactant comprises chlorine argon plasma.

18. The method of claim 16 , wherein exposing the sidewalls to the chlorine reactant and/or the ionized argon gas is less than 100 ms.

19. The method of claim 16 , wherein the second atomic layer deposition process treats the sidewalls with a chlorinated III-V compound.

Assignees

• California Inst Of Techn

Inventors

• Hill Cory J
• Greer Harold Frank

Classifications

• H10F39/184 Primary

  Infrared image sensors · CPC title

• H10F39/021

  of image sensors having active layers comprising only Group III-V materials, e.g. GaAs, AlGaAs or InP · CPC title

• H10F39/028 Primary

  performed after manufacture of the image sensors, e.g. annealing, gettering of impurities, short-circuit elimination or recrystallisation · CPC title