Insulated gate structure, wide bandgap material power device with the same and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-12426343-B2
Application number	US-202117912221-A
Country	US
Kind code	B2
Filing date	Feb 25, 2021
Priority date	Mar 17, 2020
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

An insulated gate structure includes a wide bandgap material layer having a channel region of a first conductivity type. A gate insulating layer is arranged directly on the channel region and has a first nitride layer that is arranged directly on the channel region. The gate insulating layer has a concentration of carbon atoms that is less than 1018 atoms/cm−3 at a distance of 3 nm from an interface between the wide bandgap material layer and the first nitride layer. An electrically conductive gate electrode layer overlies the gate insulating layer so that the gate electrode layer is separated from the wide bandgap material layer by the gate insulating layer.

First claim

The invention claimed is:

1. An insulated gate structure comprising:
a wide bandgap material layer comprising a channel region of a first conductivity type;
a gate insulating layer arranged directly on the channel region, the gate insulating layer comprising a first nitride layer that is arranged directly on the channel region, wherein the gate insulating layer has a concentration of carbon atoms that is less than 10 18 atoms/cm −3 at a distance of 3 nm from an interface between the wide bandgap material layer and the first nitride layer and wherein the first nitride layer comprises a stoichiometric silicon nitride layer, an aluminum nitride layer, a boron nitride layer or a phosphorous nitride layer; and
an electrically conductive gate electrode layer over the gate insulating layer so that the gate electrode layer is separated from the wide bandgap material layer by the gate insulating layer.

2. The insulated gate structure according to claim 1 , wherein the first nitride layer has a thickness that is less than 20 nm.

3. The insulated gate structure according to claim 1 , wherein the first nitride layer has a thickness that is less than 5 nm.

4. The insulated gate structure according to claim 1 , wherein the gate insulating layer further comprises an intermediate insulating layer on the first nitride layer, wherein the intermediate insulating layer is made of a material different from that of the first nitride layer.

5. The insulated gate structure according to claim 4 , further comprising a second nitride layer is arranged directly on the intermediate insulating layer so that the intermediate insulating layer is sandwiched between the first nitride layer and the second nitride layer.

6. The insulated gate structure according to claim 4 , wherein the wide bandgap material layer is a silicon carbide layer and the intermediate insulating layer comprises a high-k dielectric layer that has a dielectric constant higher than that of Si 3 N 4 .

7. The insulated gate structure according to claim 4 , wherein the wide bandgap material layer is a silicon carbide layer and the intermediate insulating layer comprises a silicon oxide layer.

8. A wide bandgap material power device comprising:
a wide bandgap material layer comprising a channel region of a first conductivity type and a source region and a drain region of a second conductivity different than the first conductivity type, the source region spaced from the drain region by the channel region;
a gate insulating layer arranged directly on the channel region, the gate insulating layer comprising a first nitride layer that is arranged directly on the channel region, wherein the gate insulating layer has a concentration of carbon atoms that is less than 10 18 atoms/cm −3 at a distance of 3 nm from an interface between the wide bandgap material layer and the first nitride layer and wherein the first nitride layer comprises a stoichiometric silicon nitride layer, an aluminum nitride layer, a boron nitride layer or a phosphorous nitride layer; and
an electrically conductive gate electrode layer over the gate insulating layer so that the gate electrode layer is separated from the wide bandgap material layer by the gate insulating layer.

9. The device according to claim 8 , wherein:
the wide bandgap material layer is a silicon carbide layer;
the gate insulating layer further comprises an intermediate insulating layer on the first nitride layer and a second nitride layer arranged directly on the intermediate insulating layer; and
the intermediate insulating layer comprises a high-k dielectric layer that has a dielectric constant higher than that of Si 3 N 4 .

10. A method for manufacturing an insulated gate structure, the method comprising:
forming a gate insulating layer arranged directly on a channel region of a wide bandgap material layer, the gate insulating layer comprising a first nitride layer that is arranged directly on the channel region, wherein the gate insulating layer has a concentration of carbon atoms that is less than 10 18 atoms/cm −3 at a distance of 3 nm from an interface between the wide bandgap material layer and the first nitride layer and wherein the first nitride layer comprises a stoichiometric silicon nitride layer, an aluminum nitride layer, a boron nitride layer or a phosphorous nitride layer; and
forming an electrically conductive gate electrode layer over the gate insulating layer.

11. The method according to claim 10 , wherein forming the gate insulating layer comprises:
depositing a preliminary layer directly on the channel region of the wide bandgap material layer, wherein the preliminary layer comprises silicon, aluminum, boron, or phosphorous or any combination thereof; and
nitriding the preliminary layer in a nitrogen containing atmosphere to form the first nitride layer.

12. The method according to claim 11 , wherein the nitriding is performed at a temperature in a range between 800° C. and 1400° C.

13. The method according to claim 11 , wherein the preliminary layer comprises an amorphous silicon layer.

14. The method according to claim 11 , wherein depositing the preliminary layer comprises depositing a layer having a thickness of less than 15 nm.

15. The method according to claim 14 , wherein depositing the preliminary layer comprises depositing a layer having a thickness of less than 3.75 nm.

16. The method according to claim 11 , wherein forming the gate insulating layer further comprises forming a second nitride layer on the preliminary layer before the nitriding.

17. The method according to claim 11 , wherein forming the gate insulating layer further comprises forming a silicon oxide layer on the preliminary layer before the step of nitriding.

18. The method according to claim 11 , wherein forming the gate insulating layer further comprises forming an intermediate insulating layer on the first nitride layer.

19. The method according to claim 18 , wherein forming the gate insulating layer further comprises forming a second nitride layer on the intermediate insulating layer so that the intermediate insulating layer is sandwiched between the first nitride layer and the second nitride layer.

20. The method according to claim 18 , wherein the intermediate insulating layer is a high-k dielectric layer having a dielectric constant higher than that of Si 3 N 4 .

Assignees

• Hitachi Energy Ltd
• Hitachi Energy Switzerland Ag

Inventors

• Knoll Lars
• Wirths Stephan
• Mihaila Andrei

Classifications

• H10D64/01358

  the insulator being formed after the semiconductor body, the semiconductor being a Group III-V material · CPC title

• H10D64/01366

  the semiconductor being silicon carbide · CPC title

• H10D64/01364

  the semiconductor being diamond, semiconducting diamond-like carbon or graphene · CPC title

• H10D64/011 Primary

  of electrodes ohmically coupled to a semiconductor · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title