Forming SiC MOSFETs with high channel mobility by treating the oxide interface with cesium ions

Patent metadata

Field	Value
Publication number	US-9984894-B2
Application number	US-201113196994-A
Country	US
Kind code	B2
Filing date	Aug 3, 2011
Priority date	Aug 3, 2011
Publication date	May 29, 2018
Grant date	May 29, 2018

Abstract

Methods of forming a semiconductor structure include providing an insulation layer on a semiconductor layer and diffusing cesium ions into the insulation layer from a cesium ion source outside the insulation layer. A MOSFET including an insulation layer treated with cesium ions may exhibit increased inversion layer mobility.

First claim

That which is claimed is:

1. A method of forming a semiconductor structure, comprising:
providing an insulation layer on a semiconductor layer;
depositing a cesium ion source on the insulation layer; and
diffusing cesium ions from the cesium ion source into the insulation layer,
wherein diffusing the cesium ions from the cesium ion source into the insulation layer comprises annealing the insulation layer,
wherein depositing the cesium ion source on the insulation layer comprises boiling the insulation layer in a CsCl solution,
wherein providing the insulation layer on the semiconductor layer comprises forming and/or annealing the insulation layer in an environment containing nitrogen to nitridate the insulation layer and provide a nitridated insulation layer before depositing the cesium ion source on the insulation layer,
wherein diffusing the cesium ions from the cesium ion source into the insulation layer comprises diffusing cesium ions into the nitridated insulation layer, and
wherein, responsive to diffusing the cesium ions from the cesium ion source into the nitridated insulation layer, the semiconductor structure has a channel mobility of at least 40 cm 2 /V-s at an applied electric field of 3 MV/cm.

2. The method of claim 1 , wherein diffusing the cesium ions into the insulation layer comprises diffusing the cesium ions to an interface between the insulation layer and the semiconductor layer.

3. The method of claim 1 , wherein boiling the insulation layer in the CsCl solution comprises boiling the insulation layer in a 0.1 M to 1 M aqueous CsCl solution for 1 minute to 60 minutes at a temperature of about 90° C. to about 100° C.

4. The method of claim 1 , wherein annealing the insulation layer comprises annealing the insulation layer at a temperature between about 700° C. and about 1000° C.

5. The method of claim 1 , wherein providing the insulation layer comprises thermally oxidizing the semiconductor layer.

6. The method of claim 1 , wherein providing the insulation layer comprises depositing the insulation layer on the semiconductor layer.

7. The method of claim 1 , wherein the semiconductor layer comprises silicon carbide and the insulation layer comprises silicon dioxide.

8. The method of claim 1 , wherein the semiconductor layer comprises polysilicon, amorphous silicon or gallium nitride.

9. The method of claim 1 , wherein the nitridated insulation layer has a concentration of cesium ions of at least about 3×10 14 cm −2 .

10. A method of forming a field effect transistor device, comprising:
providing a semiconductor layer;
forming spaced apart source and drain regions in the semiconductor layer, the source and drain regions defining a channel region in the semiconductor layer;
providing an insulation layer on the semiconductor layer over the channel region;
depositing a cesium ion source on the insulation layer;
diffusing cesium ions from the cesium ion source into the insulation layer;
forming a gate electrode on the insulation layer; and
forming a contact on the source and drain regions,
wherein diffusing the cesium ions from the cesium ion source into the insulation layer comprises annealing the insulation layer,
wherein depositing the cesium ion source on the insulation layer comprises boiling the insulation layer in a CsCl solution,
wherein providing the insulation layer on the semiconductor layer over the channel region comprises forming and/or annealing the insulation layer in an environment containing nitrogen to nitridate the insulation layer and provide a nitridated insulation layer before depositing the cesium ion source on the insulation layer,
wherein diffusing the cesium ions from the cesium ion source into the insulation layer comprises diffusing cesium ions into the nitridated insulation layer, and
wherein, responsive to diffusing the cesium ions from the cesium ion source into the nitridated insulation layer, the channel region has a channel mobility of at least 40 cm 2 /V-s at an applied electric field of 3 MV/cm.

11. The method of claim 10 , wherein diffusing the cesium ions from the cesium ion source into the insulation layer comprises diffusing the cesium ions to an interface between the insulation layer and the semiconductor layer.

12. The method of claim 10 , wherein boiling the insulation layer in the CsCl solution comprises boiling the insulation layer in a 0.1 M aqueous CsCl solution for 10 minutes at a temperature of about 95° C.

13. The method of claim 10 , wherein annealing the insulation layer comprises annealing the insulation layer at a temperature between about 700° C. and about 1000° C.

14. The method of claim 10 , wherein the semiconductor layer comprises silicon carbide and the insulation layer comprises silicon dioxide.

15. The method of claim 10 , wherein the semiconductor layer comprises polysilicon, amorphous silicon or gallium nitride.

16. The method of claim 10 , wherein the nitridated insulation layer has a concentration of cesium ions of at least about 3×10 14 cm −2 .

Assignees

• Dhar Sarit
• Ryu Sei Hyung
• Agarwal Anant
• Williams John Robert
• Cree Inc
• Univ Auburn

Inventors

• Dhar Sarit
• Ryu Sei-Hyung
• Agarwal Anant
• Williams John Robert

Classifications

• H10D64/01366

  the semiconductor being silicon carbide · CPC title

• H10P32/20 Primary

  Diffusion for doping of insulating layers · CPC title

• H10D30/0291

  of vertical DMOS [VDMOS] FETs · CPC title

• H10D30/662

  having a drift region having a doping concentration that is higher between adjacent body regions relative to other parts of the drift region · CPC title

• H01L29/78

  Electricity · mapped topic