Semiconductor device with interlayer insulation structure including metal-organic framework layer and method of manufacturing the same
US-2023013343-A1 · Jan 19, 2023 · US
US12426264B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12426264-B2 |
| Application number | US-202217989061-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 17, 2022 |
| Priority date | Nov 23, 2021 |
| Publication date | Sep 23, 2025 |
| Grant date | Sep 23, 2025 |
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A semiconductor device includes a lower structure, a stack structure including gate layers and interlayer insulating layers alternately stacked on the lower structure in a first direction, and a channel structure in a channel hole passing through the stack structure. The channel structure includes a variable resistance material layer in the channel hole, a data storage material layer between the variable resistance material layer and a sidewall of the channel hole, and a channel layer between the data storage material layer and the sidewall of the channel hole, the channel layer includes a first element, the variable resistance material layer includes a second element, different from the first element, oxygen, and oxygen vacancies, and the data storage material layer includes the first element, the second element, oxygen, and oxygen vacancies.
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What is claimed is: 1. A semiconductor device comprising: a lower structure; a stack structure including gate layers and interlayer insulating layers alternately stacked on the lower structure in a first direction; and a channel structure in a channel hole that passes through the stack structure, wherein the channel structure includes a variable resistance material layer in the channel hole, a data storage material layer between the variable resistance material layer and a sidewall of the channel hole, and a channel layer between the data storage material layer and the sidewall of the channel hole, the channel layer includes a first element, the variable resistance material layer includes a second element, different from the first element, and oxygen, and the variable resistance material layer has oxygen vacancies, and the data storage material layer includes the first element, the second element, and oxygen, and the data storage material layer has oxygen vacancies. 2. The semiconductor device of claim 1 , wherein the first element includes silicon (Si), and the second element includes at least one of hafnium (Hf), aluminum (Al), titanium (Ti), or lanthanum (La). 3. The semiconductor device of claim 1 , wherein a first concentration of the oxygen vacancies in the data storage material layer is greater than a second concentration of the oxygen vacancies in the variable resistance material layer. 4. The semiconductor device of claim 1 , wherein the data storage material layer includes a material in which the channel layer and the variable resistance material layer are combined in a ratio of greater than or equal to 1 to 1.6 and less than or equal to 1 to 5.6. 5. The semiconductor device of claim 1 , wherein the channel layer and the data storage material layer have uniform thicknesses. 6. The semiconductor device of claim 1 , wherein a thickness of the data storage material layer is less than a thickness of the variable resistance material layer. 7. The semiconductor device of claim 6 , wherein a thickness of the data storage material layer is in a range of 1 nm to 3 nm, and a thickness of the variable resistance material layer is in a range of 7 nm to 20 nm. 8. The semiconductor device of claim 1 , wherein the channel structure further includes a buried insulating layer extending in the first direction, a conductive pad on the buried insulating layer and in contact with the channel layer, and a dielectric layer between the channel layer and the stack structure, and the variable resistance material layer covers a side surface of and a bottom surface of the buried insulating layer. 9. The semiconductor device of claim 1 , wherein the channel structure includes first portions on the same height level as the gate layers and second portions on the same height level as the interlayer insulating layers, and a first distance from a central axis of the channel structure in the first direction to the data storage material layer in each of the first portions is greater than a second distance from the central axis to the data storage material layer in each of the second portions. 10. The semiconductor device of claim 9 , wherein the data storage material layer includes a bent portion in the first portions. 11. The semiconductor device of claim 9 , wherein the variable resistance material layer includes protrusions protruding from the first portions toward the gate layers, and the data storage material layer covers the protrusions. 12. The semiconductor device of claim 1 , wherein the gate layers include a first gate portion in a region adjacent to the channel structure, and a remaining second gate portion, wherein the first gate portion includes doped polysilicon, and the second gate portion includes a metallic material. 13. The semiconductor device of claim 1 , wherein the lower structure includes a lower substrate, circuit elements on the lower substrate, and an upper substrate on the circuit elements, and the channel structure is in contact with the upper substrate and is electrically connected to at least a portion of the circuit elements. 14. A semiconductor device comprising: a lower structure including a substrate; a stack structure including gate layers and interlayer insulating layers alternately stacked on the lower structure in a vertical direction, perpendicular to the substrate; and a channel structure in a channel hole passing through the stack structure, wherein the channel structure includes a variable resistance material layer in the channel hole, a data storage material layer between the variable resistance material layer and a sidewall of the channel hole, and a channel layer between the data storage material layer and the sidewall of the channel hole, the channel structure includes first portions on the same height level as the gate layers and second portions on the same height level as the interlayer insulating layers, in a horizontal direction that is perpendicular to the vertical direction, a width of each of the first portions is wider than a width of each of the second portions, the variable resistance material layer includes a transition metal oxide having oxygen vacancies, the data storage material layer includes a transition metal-silicon oxide having oxygen vacancies, the channel layer includes a semiconductor material, and a first concentration of oxygen vacancies in the data storage material layer is greater than a second concentration of oxygen vacancies in the variable resistance material layer. 15. The semiconductor device of claim 14 , wherein the channel layer includes a first element, the variable resistance material layer includes a second element, different from the first element, and oxygen, and the data storage material layer includes the first element, the second element, and oxygen. 16. The semiconductor device of claim 14 , wherein the transition metal oxide includes at least one of hafnium oxide (HfOx), aluminum oxide (AlOx), hafnium-aluminum oxide (HfAlOx), titanium oxide (TiOx), or lanthanum oxide (LaOx), and the semiconductor material includes polysilicon. 17. The semiconductor device of claim 14 , wherein a first thickness of the data storage material layer is less than a second thickness of the variable resistance material layer. 18. The semiconductor device of claim 14 , wherein the channel hole has a vertical opening extending in the vertical direction, and horizontal openings extending from the vertical opening in the horizontal direction, and each of the channel layer and the data storage material layer continuously extends along sidewalls of the vertical opening and the horizontal openings. 19. A data storage system comprising: a semiconductor storage device including a lower substrate, circuit elements on the lower substrate, a lower structure on the circuit elements and including an upper substrate, a stack structure including gate layers and interlayer insulating layers alternately stacked on the lower structure in a first direction, the semiconductor storage device further including a channel structure in a channel hole passing through the stack structure, and an input/output pad electrically connected to the circuit elements; and a controller electrically connected to the semiconductor storage device through the input/output pad and configured to control the semiconductor storage device, wherein the channel structure includes a variable resistance material layer in the channel hole, a data storage material layer between the variable
Cross-sectional shapes or dispositions of interconnections · CPC title
with cell select transistors, e.g. NAND · CPC title
characterised by the top-view layout · CPC title
with a cell select transistor, e.g. NAND · CPC title
the channels comprising vertical portions, e.g. U-shaped channels · CPC title
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