Semiconductor memory device and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-12426243-B2
Application number	US-202217735838-A
Country	US
Kind code	B2
Filing date	May 3, 2022
Priority date	May 27, 2021
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

A semiconductor memory device includes a device isolation pattern on a substrate and defining a first active section, a first storage node pad on the first active section, a word line in the substrate and extending across the first active section, a bit line on the first storage node pad and crossing over the word line, a storage node contact on one side of the bit line and adjacent to the first storage node pad, and an ohmic layer between the storage node contact and the first storage node pad. A bottom surface of the ohmic layer is rounded.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a device isolation pattern on a substrate and defining a first active section;
a first storage node pad on the first active section;
a word line in the substrate and extending across the first active section;
a bit line on the first storage node pad and crossing over the word line;
a storage node contact on one side of the bit line and adjacent to the first storage node pad; and
an ohmic contact layer between the storage node contact and the first storage node pad,
wherein a bottom surface of the storage node contact is rounded,
wherein a bottom surface of the ohmic contact layer is rounded, and
wherein the ohmic contact layer directly contacts the first storage node pad and directly contacts only a partial portion of the bottom surface of the storage node contact.

2. The semiconductor memory device of claim 1 , further comprising:
a second active section defined by the device isolation pattern and adjacent to the first active section;
a second storage node pad on the second active section;
a pad separation pattern between the first storage node pad and the second storage node pad; and
a word-line capping pattern on the word line,
wherein the pad separation pattern directly contacts a topmost surface of the word-line capping pattern.

3. The semiconductor memory device of claim 2 , further comprising:
a first subsidiary dielectric pattern between the first storage node pad and the pad separation pattern; and
a second subsidiary dielectric pattern between the second storage node pad and the pad separation pattern,
wherein the pad separation pattern is between the first subsidiary dielectric pattern and the second subsidiary dielectric pattern, and
wherein each of the first subsidiary dielectric pattern and the second subsidiary dielectric pattern includes a material different from a material of the pad separation pattern.

4. The semiconductor memory device of claim 2 ,
wherein the pad separation pattern contacts a top surface of the first storage node pad and a top surface of the second storage node pad.

5. The semiconductor memory device of claim 4 , further comprising:
a bit-line contact between the bit line and the second active section,
wherein the second active section is below the bit line, and
wherein a top surface of the bit-line contact is at a level that is the same as a level of a top surface of the pad separation pattern.

6. The semiconductor memory device of claim 2 ,
wherein a topmost surface of the first storage node pad, a topmost surface of the second storage node pad, and a topmost surface of the pad separation pattern are at a same level as each other.

7. The semiconductor memory device of claim 2 ,
wherein the bit line crosses over the pad separation pattern,
wherein the semiconductor memory device further comprises:
a first spacer that covers a sidewall of the bit line; and
a first dielectric layer, a second dielectric layer, and a third dielectric layer that are sequentially interposed between the pad separation pattern and the bit line,

wherein the first dielectric layer directly contacts the pad separation pattern,
wherein the second dielectric layer and the third dielectric layers are between the first dielectric layer and the bit line,
wherein a sidewalls of the second dielectric layer and a sidewall of the third dielectric layers are aligned with-a the sidewall of the bit line, and
wherein a sidewall of the first dielectric layer is aligned with a sidewall of the first spacer.

8. The semiconductor memory device of claim 1 ,
wherein the storage node contact is formed of a metal and a metal nitride.

9. The semiconductor memory device of claim 1 , further comprising:
a second active section defined by the device isolation pattern and adjacent to the first active section, the second active section being below the bit line; and
a bit-line contact between the bit line and the second active section,
wherein the device isolation pattern exposes a first lateral surface of the second active section of the substrate, and wherein the bit-line contact is in contact with the first lateral surface of the second active section.

10. The semiconductor memory device of claim 9 ,
wherein the second active section of the substrate has a second lateral surface that is exposed by the device isolation pattern and is opposite to the first lateral surface, and
wherein the bit-line contact is further in contact with the second lateral surface of the second active section.

11. The semiconductor memory device of claim 1 , further comprising:
a second active section defined by the device isolation pattern and adjacent to the first active section, the second active section being below the bit line; and
a bit-line contact between the bit line and the second active section,
wherein a bottom surface of the bit-line contact has a first width, and a top surface of the bit-line contact has a second width, the first width being greater than the second width.

12. The semiconductor memory device of claim 11 ,
wherein an intermediate portion of the bit-line contact is a portion of the bit-line contact between the bottom surface of the bit-line contact and the top surface of the bit-line contact, and
wherein a third width of the intermediate portion of the bit-line contact is greater than the first width of the bottom surface of the bit-line contact.

13. The semiconductor memory device of claim 1 , further comprising:
a second active section defined by the device isolation pattern and adjacent to the first active section, the second active section being below the bit line; and
a bit-line contact between the bit line and the second active section,
wherein a bottom end of the first storage node pad is at a level-a as same as or higher than a level of a bottom end of the bit-line contact.

14. The semiconductor memory device of claim 1 ,
wherein the device isolation pattern exposes a first lateral surface of the first active section of the substrate, and
wherein the first storage node pad is in contact with the first lateral surface of the first active section.

15. The semiconductor memory device of claim 14 ,
wherein the first active section of the substrate has a second lateral surface that is exposed by the device isolation pattern and is opposite to the first lateral surface of the first active section, and
wherein the first storage node pad is in contact with the second lateral surface of the first active section.

16. The semiconductor memory device of claim 1 , further comprising:
a second active section defined by the device isolation pattern and adjacent to the first active section, the second active section being below the bit line;
a bit-line contact between the bit line and the second active section; and
a contact dielectric pattern between the first storage node pad and a lower portion of the bit-line contact,
wherein the contact dielectric pattern includes a material whose dielectric constant is less than a dielectric constant of silicon nitride.

17. The semiconductor memory device of claim 16 , further comprising:
a buried dielectric pattern between the contact dielectric pattern and an upper portion of the bit-line contact,
wherein the buried dielectric pattern has a downwardly-decreasing width.

18. The semiconductor memory device of claim 16 , wherein
wherein the contact dielectric pattern extends downwardly below the bit line,
wherein the contact dielectric pattern has a first height between the

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Eunjung
• Kim Hyo-Sub
• Choi Jay-Bok
• Ahn Yongseok
• Ahn Junhyeok
• Lee Kiseok
• Lee Myeong-Dong
• Choi Yoonyoung

Classifications

• H10B12/485

  Bit line contacts · CPC title

• H10B12/34

  the transistor being at least partially in a trench in the substrate · CPC title

• H10B12/05

  Making the transistor · CPC title

• H10B12/315 Primary

  with the capacitor higher than a bit line · CPC title

• H10B12/0335 Primary

  Making a connection between the transistor and the capacitor, e.g. plug · CPC title