Semiconductor device and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9293336-B2
Application number	US-201414258107-A
Country	US
Kind code	B2
Filing date	Apr 22, 2014
Priority date	Apr 24, 2013
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

A semiconductor device includes a storage node contact on a substrate, and a lower electrode on the storage node contact, a lower sidewall of the lower electrode being covered by a contact residue of a same material as the storage node contact.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a storage node contact on a substrate;
a lower electrode on the storage node contact, a lower sidewall of the lower electrode being covered by a contact residue of a same material as the storage node contact, and an outermost surface of the contact residue being horizontally spaced apart from a corresponding outermost surface of the storage node contact; and
a first protection layer surrounding the lower sidewall of the lower electrode and the contact residue, a lateral surface of the first protection layer contacting lateral surfaces of the lower sidewall of the lower electrode and of the contact residue, a top surface of the first protection layer being higher than a top end of the contact residue.

2. The semiconductor device as claimed in claim 1 , further comprising an ohmic layer between the lower electrode and the storage node contact, the top surface of the first protection layer being higher than a top end of the ohmic layer.

3. The semiconductor device as claimed in claim 1 , wherein:
the storage node contact includes a plurality of storage node contacts; and
the semiconductor device further comprises:
a filling insulating layer between storage node contacts adjacent to each other and covered by the first protection layer, and
an etch stop layer between the first protection layer and the filling insulating layer.

4. The semiconductor device as claimed in claim 1 , further comprising at least one supporting layer contacting an upper sidewall of the lower electrode.

5. The semiconductor device as claimed in claim 4 , wherein:
the supporting layer includes a metal oxide layer; and
the semiconductor device further comprises a second protection layer contacting at least one of a top surface and a bottom surface of the supporting layer.

6. The semiconductor device as claimed in claim 4 , wherein the supporting layer and the first protection layer include insulating layers.

7. The semiconductor device as claimed in claim 1 , wherein a top surface of the storage node contact is concave.

8. The semiconductor device as claimed in claim 1 , further comprising:
a dielectric layer covering a sidewall and a top surface of the lower electrode; and
an upper electrode covering the dielectric layer, the dielectric layer extending to cover a sidewall of the contact residue.

9. A semiconductor device, comprising:
a storage node contact on a substrate;
a lower electrode on the storage node contact;
a contact residue of a same material as the storage node contact and extending from the storage node contact along a lower sidewall of the lower electrode, an outermost surface of the contact residue and an outermost surface of an upper sidewall of the lower electrode being level with each other; and
a first protection layer surrounding an upper portion of the contact residue,
wherein the first protection layer is in direct contact with a lateral surface of the contact residue and in direct contact with a lateral surface of a portion of the lower electrode, the lateral surfaces of the contact residue and the lower electrode being the level outermost surfaces of the contact residue and the lower electrode.

10. The semiconductor device as claimed in claim 9 , further comprising:
a dielectric layer on a sidewall of the lower electrode, the first protection layer separating the dielectric layer from the contact residue; and
an upper electrode on the dielectric layer, the dielectric layer separating the first protection layer from the upper electrode and from the lower electrode.

11. The semiconductor device as claimed in claim 9 , wherein the contact residue is integral with the storage node contact and defines an empty, volumetric space above the storage node contact, a lower end of the lower electrode being insertable into the volumetric space, and a width between opposite outermost surfaces of the contact residue being smaller than a width between opposite outermost surfaces of the storage node contact.

12. The semiconductor device as claimed in claim 9 , wherein the level outermost surfaces of the contact residue and lower electrode define openings between adjacent lower electrodes, respective dielectric layers and upper electrodes being positioned in the defined openings.

13. The semiconductor device as claimed in claim 9 , further comprising:
a dielectric layer on a sidewall of the lower electrode, the dielectric layer being in direct contact with the contact residue and in direct contact with a portion of the lower electrode; and
an upper electrode on the dielectric layer.

14. A method of fabricating a semiconductor device, the method comprising:
forming a storage node contact on a substrate;
sequentially forming a first protection layer and a mold layer that cover the storage node contact;
successively patterning the mold layer and the first protection layer to form a contact hole exposing the storage node contact; and
forming a lower electrode on the storage node contact filling the contact hole,
wherein, when the contact hole is formed, an upper portion of the storage node contact is dug, such that a contact residue of a same material as the storage node contact is formed on a lower sidewall of the contact hole, and an outermost surface of the contact residue being horizontally spaced apart from a corresponding outermost surface of the storage node contact,
wherein the first protection layer surrounds a lower sidewall of the lower electrode and the contact residue, a lateral surface of the first protection layer contacting lateral surfaces of the lower sidewall of the lower electrode and of the contact residue; and
wherein the contact residue covers a lower sidewall of the lower electrode, such that a height of a top surface of the first protection layer is higher than a top end of the contact residue.

15. The method as claimed in claim 14 , wherein the mold layer is formed of poly-silicon or single-crystalline silicon, and the storage node contact is formed of metal.

16. The method as claimed in claim 14 , wherein the first protection layer is formed of at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon-carbon nitride layer, or a silicon-carbon oxynitride layer.

17. The method as claimed in claim 14 , further comprising forming a supporting layer on the mold layer, the contact hole being formed by successively patterning the supporting layer, the mold layer, and the first protection layer.

18. The method as claimed in claim 17 , wherein:
the supporting layer is formed of a metal oxide layer, and
the method further comprises forming a second protection layer between the supporting layer and the mold layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yang Sangryol
• Jung Soonwook
• Kim Kyoungseob
• You Youngsub
• Chung Byunghong
• Choi Hanmei

Classifications

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10P14/40 Primary

  of conductive or resistive materials · CPC title

• H10D64/035 Primary

  comprising conductor-insulator-conductor-insulator-semiconductor structures · CPC title

• H10B12/315 Primary

  with the capacitor higher than a bit line · CPC title

• H01L21/76805

  Electricity · mapped topic