Package with a substrate comprising embedded escape interconnects and surface escape interconnects

Patent metadata

Field	Value
Publication number	US-12424559-B2
Application number	US-202217684327-A
Country	US
Kind code	B2
Filing date	Mar 1, 2022
Priority date	Mar 1, 2022
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

A package that includes a substrate, a first integrated device coupled to the substrate, and a second integrated device coupled to the substrate. The substrate includes at least one dielectric layer, and a plurality of interconnects comprising a plurality of escape interconnects. The plurality of escape interconnects includes a first embedded escape interconnect, a second embedded escape interconnect, and a third escape interconnect located between the first embedded escape interconnect and the second embedded escape interconnect.

First claim

The invention claimed is:

1. A package comprising:
a substrate comprising:
at least one dielectric layer;
a solder resist layer coupled to and touching a surface of the at least one dielectric layer; and
a plurality of interconnects comprising a plurality of escape interconnects, wherein the plurality of escape interconnects comprises:
a first embedded escape interconnect located at least partially in the at least one dielectric layer, wherein the first embedded escape interconnect touches the solder resist layer, wherein the first embedded escape interconnect comprises a first embedded escape pad and a first embedded trace;
a second embedded escape interconnect located at least partially in the at least one dielectric layer, wherein the second embedded escape interconnect touches the solder resist layer, wherein the second embedded escape interconnect comprises a second embedded escape pad and a second embedded escape trace; and
a third escape interconnect located between the first embedded escape interconnect and the second embedded escape interconnect,
wherein the third escape interconnect is located on the surface of the at least one dielectric layer that touches the solder resist layer,
wherein a side surface of the third escape interconnect touches the solder resist layer, and
wherein the third escape interconnect comprises a first surface escape pad and a first surface escape trace;

a first integrated device coupled to the substrate; and
a second integrated device coupled to the substrate.

2. The package of claim 1 ,
wherein the third escape interconnect is located on a different metal layer than the first embedded escape interconnect and the second embedded escape interconnect,
wherein a top surface of the first embedded escape interconnect touches the solder resist layer;
wherein a top surface of the second embedded escape interconnect touches the solder resist layer; and
wherein the solder resist layer includes a different material from the at least one dielectric layer.

3. The package of claim 1 , wherein the second integrated device is configured to be electrically coupled to the first integrated device through the plurality of escape interconnects.

4. The package of claim 1 ,
wherein the first integrated device is coupled to the first embedded escape pad through at least a first solder interconnect such that the first solder interconnect touches the first embedded escape pad,
wherein the first integrated device is coupled to the second embedded escape pad through at least a second solder interconnect such that the second solder interconnect touches the second embedded escape pad, and
wherein the first integrated device is coupled to the first surface escape pad through at least a third solder interconnect such that the third solder interconnect touches the first surface escape pad.

5. The package of claim 4 , wherein the second integrated device is configured to be electrically coupled to the first integrated device through the first embedded escape pad, the first embedded escape trace, the second embedded escape pad, the second embedded escape trace, the first surface escape pad and the first surface escape trace.

6. The package of claim 5 ,
wherein a first electrical path between the first integrated device and the second integrated device includes the first embedded escape pad and the first embedded escape trace,
wherein a second electrical path between the first integrated device and the second integrated device includes the second embedded escape pad and the second embedded escape trace, and
wherein a third electrical path between the first integrated device and the second integrated device includes the first surface escape pad and the first surface escape trace.

7. The package of claim 1 , wherein a minimum width of the first embedded escape interconnect, the second embedded escape interconnect and the third escape interconnect is in a range of about 10-15 micrometers.

8. The package of claim 1 ,
wherein a first minimum spacing between the first embedded escape interconnect and the third escape interconnect is in a first range of about 10-15 micrometers, and
wherein a second minimum spacing between the second embedded escape interconnect and the third escape interconnect is in a second range of about 10-15 micrometers.

9. The package of claim 1 , wherein the first integrated device includes a first chiplet and the second integrated device includes a second chiplet.

10. The package of claim 1 ,
wherein a portion of the third escape interconnect is located parallel to a portion of the first embedded escape interconnect and a portion of the second embedded escape interconnect, and
wherein the third escape interconnect is located on a metal layer that is directly adjacent to a metal layer comprising the first embedded escape interconnect and the second embedded escape interconnect,
wherein the third escape interconnect being located between the first embedded escape interconnect and the second embedded escape interconnect means that the third escape interconnect is directly adjacent to the first embedded escape interconnect, and that the third escape interconnect is directly adjacent to the second embedded escape interconnect; and
wherein the first embedded escape interconnect, the second embedded escape interconnect and the third escape interconnect vertically overlap with the first integrated device and the second integrated device.

11. A package comprising:
a substrate comprising:
at least one dielectric layer;
a solder resist layer coupled to and touching a surface of the at least one dielectric layer;
means for first embedded escape interconnection located at least partially in the at least one dielectric layer, wherein the means for first embedded escape interconnection touches the solder resist layer, wherein the means for first embedded escape interconnection comprises a first embedded escape pad and a first embedded trace;
means for second embedded escape interconnection located at least partially in the at least one dielectric layer, wherein the means for second embedded escape interconnection touches the solder resist layer, wherein the means for second embedded escape interconnection comprises a second embedded escape pad and a second embedded escape trace; and
means for surface escape interconnection, wherein the means for surface escape interconnection is located between the means for first embedded escape interconnection and the means for second embedded escape interconnection,
wherein the means for surface escape interconnection is located on the surface of the at least one dielectric layer that touches the solder resist layer,
wherein a side surface of the means for surface escape interconnection touches the solder resist layer, and
wherein the means for surface escape interconnection comprises a first surface escape pad and a first surface escape trace;

a first integrated device coupled to the substrate; and
a second integrated device coupled to the substrate.

12. The package of claim 11 ,
wherein the means for surface escape interconnection comprises an intermediate escape interconnect that is located on a different metal layer than the first embedded escape interconnection and the second embedded escape interconnection, and
wherein the solder resist layer includes a different material from the at least one dielectric layer.

13. The package of claim 11 , wherein the second integrated device is configured to be electrically coupled to the first integrated device through the means for first embedded escape interconnection, the means for second embedded escape inter

Assignees

• Qualcomm Inc

Inventors

• Kang Kuiwon
• We Hong Bok
• Kim Michelle Yejin

Classifications

• H10W70/6565

  recessed into the surface of the package substrates, interposers, or redistribution layers · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/611 Primary

  for connecting multiple chips together · CPC title

• H10W70/093

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

• H10W70/05

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title