Power semiconductor module

Patent metadata

Field	Value
Publication number	US-12424533-B2
Application number	US-202318302825-A
Country	US
Kind code	B2
Filing date	Apr 19, 2023
Priority date	Apr 22, 2022
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

A power semiconductor module includes a first and second insulating substrate, which is arranged parallel to and at a distance from the first insulating substrate. The first insulating substrate and the second insulating substrate each include an insulating layer, an inner metallization layer, and an outer metallization layer. The power semiconductor module also includes a first cooling device, which is arranged thermally conductively on the outer metallization layer of the first insulating substrate, a second cooling device, which is arranged thermally conductively on the outer metallization layer of the second insulating substrate. The power semiconductor module also includes a power semiconductor, arranged between the first insulating substrate and the second insulating substrate. At least one of the two insulating substrates include a through-contact, by which the inner metallization layer of the corresponding insulating substrate is electrically connected to the outer metallization layer of the corresponding insulating substrate.

First claim

The invention claimed is:

1. A power semiconductor module comprising:
a first insulating substrate;
a second insulating substrate, which is arranged parallel to the first insulating substrate and at a distance from the first insulating substrate, the first insulating substrate and the second insulating substrate each comprising:
an insulating layer,
an inner metallization layer which is arranged on an inner side, facing toward an other respective insulating substrate, of the insulating layer, and
an outer metallization layer which is arranged on an outer side, facing away from the other respective insulating substrate, of the insulating layer;

a first cooling device, which is arranged thermally conductively on the outer metallization layer of the first insulating substrate;
a second cooling device, which is arranged thermally conductively on the outer metallization layer of the second insulating substrate; and
a power semiconductor, which is arranged between the first insulating substrate and the second insulating substrate and is electrically and thermally connected to the inner metallization layer of the first insulating substrate and to the inner metallization layer of the second insulating substrate,
wherein
at least one of the two insulating substrates comprise a through-contact, which extends through the insulating layer of a corresponding insulating substrate and by which the inner metallization layer of the corresponding insulating substrate is electrically connected to the outer metallization layer of the corresponding insulating substrate.

2. The power semiconductor module as claimed in claim 1 , wherein an intermediate space formed between the first insulating substrate and the second insulating substrate is filled with an electrically nonconductive material.

3. The power semiconductor module as claimed in claim 1 , comprising a terminal for the external electrical contacting of the power semiconductor module, wherein the terminal is arranged on the outer metallization layer of that insulating substrate which comprises the through-contact, and is electrically connected to the corresponding outer metallization layer.

4. The power semiconductor module as claimed in claim 3 , wherein the terminal is a first DC voltage terminal, which is configured to be connected to a first DC voltage potential of a DC voltage source, and wherein a second DC voltage terminal is provided, which is configured to be connected to a second DC voltage potential of the DC voltage source and which is arranged on the inner metallization layer of that insulating substrate on which the first DC voltage terminal is arranged, and is electrically connected to the corresponding inner metallization layer.

5. The power semiconductor module as claimed in claim 3 , wherein the terminal is a first DC voltage terminal, which is configured to be connected to a first DC voltage potential of a DC voltage source, and wherein a second DC voltage terminal is provided, which is configured to be connected to a second DC voltage potential of the DC voltage source and which extends substantially parallel to the first DC voltage terminal.

6. The power semiconductor module as claimed in claim 1 , comprising:
a third insulating substrate, which is arranged in a plane with the first insulating substrate, the third insulating substrate comprising:
an insulating layer,
an inner metallization layer which is arranged on an inner side, facing toward the second insulating substrate, of the insulating layer, and
an outer metallization layer which is arranged on an outer side, facing away from the second insulating substrate, of the insulating layer and bears thermally conductively on the first cooling device; and

a further power semiconductor, which is arranged between the third insulating substrate and the second insulating substrate and is electrically and thermally connected to the inner metallization layer of the third insulating substrate and to the inner metallization layer of the second insulating substrate.

7. The power semiconductor module as claimed in claim 6 , comprising a contact which electrically connects the inner metallization layer of the third insulating substrate to the inner metallization layer of the second insulating substrate.

Assignees

• Porsche Ag

Inventors

• Barkow Maximilian
• Fuchs Patrick
• Velic Timijan
• Eckardt Bernd
• Hofmann Maximilian
• Rauh Hubert
• Mueller Andre
• Bayer Benjamin
• Sorge Jordan

Classifications

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W40/255

  having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates · CPC title