Power module having dual-sided cooling

US10147665B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10147665-B2
Application numberUS-201715639256-A
CountryUS
Kind codeB2
Filing dateJun 30, 2017
Priority dateDec 15, 2016
Publication dateDec 4, 2018
Grant dateDec 4, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A power module having dual-sided cooling is provided with a semiconductor chip between an upper board and a lower board of the power module. In particular, the upper board includes: a first bonding layer made of a dielectric material, and a first electrode made of a copper material and provided on a first surface of the first bonding layer, and the first electrode is connected to the semiconductor chip. The lower board includes: a second bonding layer made of a dielectric material, and a second electrode made of a copper material and provided on a first surface of the second bonding layer, and the second electrode is connected to the semiconductor chip. More specifically, a thickness of the first electrode is greater than a thickness of the first bonding layer, and a thickness of the second electrode is greater than a thickness of the second bonding layer.

First claim

Opening claim text (preview).

What is claimed is: 1. A power module having dual-sided cooling and provided with first and second semiconductor chips between an upper board and a lower board, the power module comprising: the upper board including a first bonding layer made of a dielectric material, and a first electrode made of a copper material and provided on a first surface of the first bonding layer, the first electrode being connected to the first semiconductor chip; the lower board including a second bonding layer made of a dielectric material, and a second electrode made of a copper material and provided on a first surface of the second bonding layer, the second electrode being connected to the second semiconductor chip; a first spacer provided between a first output terminal and the first semiconductor chip; and a second spacer provided between a second output terminal and the second semiconductor chip, wherein a thickness of the first electrode is three times or greater than a thickness of the first bonding layer, and a thickness of the second electrode is three times or greater than a thickness of the second bonding layer, wherein the first spacer is configured such that a cross-sectional area of the first spacer increases in a direction from the first semiconductor chip toward the first output terminal, and the second spacer is configured such that a cross-sectional area of the second spacer increases in a direction from the second semiconductor chip toward the second output terminal; and wherein the first semiconductor chip and the first spacer, the first spacer and the first output terminal, the second semiconductor chip and the second spacer, and the second spacer and the second output terminal are respectively soldered together by using solder material. 2. The power module of claim 1 , wherein the first electrode includes: the first output terminal provided on the first surface of the first bonding layer; and the second output terminal provided on the first surface of the first bonding layer and spaced apart from the first output terminal, and the second electrode includes: a positive terminal provided on the first surface of the second bonding layer; a third output terminal provided on the first surface of the second bonding layer and spaced apart from the positive terminal; and a negative terminal provided on the first surface of the second bonding layer and spaced apart from both the positive terminal and the third output terminal. 3. The power module of claim 2 , wherein the first semiconductor chip is provided between the first output terminal and the positive terminal; and the second semiconductor chip is provided between the second output terminal and the third output terminal. 4. The power module of claim 3 , wherein the positive terminal and the first semiconductor chip, the third output terminal and the second semiconductor chip, are respectively soldered together by using solder material. 5. The power module of claim 3 , further comprising: a first bridge made of a copper material and configured to connect the first output terminal and the third output terminal to each other; and a second bridge made of a copper material and configured to connect the second output terminal and the negative terminal to each other, wherein the first bridge is soldered to the first output terminal and the third output terminal by using the solder material, and the second bridge is soldered to the second output terminal and the negative terminal by using the solder material. 6. The power module of claim 1 , wherein the upper board further includes a first heat dissipating plate being provided on a second surface of the first bonding layer and being in contact with a first cooler, and the lower board further includes a second heat dissipating plate being provided on a second surface of the second bonding layer and being in contact with a second cooler. 7. The power module of claim 6 , further comprising a thermal grease provided between the first heat dissipating plate and the first cooler, and between the second heat dissipating plate and the second cooler. 8. The power module of claim 1 , wherein each of the first bonding layer and the second bonding layer contains 3 to 40 wt % of an epoxy compound and 50 to 95 wt % of ceramic.

Assignees

Inventors

Classifications

  • characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

  • having another interconnection being formed by a cover plate parallel to the conductive base, e.g. sandwich type · CPC title

  • characterised by changes in properties of the die-attach connectors during connecting · CPC title

  • Die-attach connectors · CPC title

  • for connecting multiple chips together · CPC title

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Frequently asked questions

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What does patent US10147665B2 cover?
A power module having dual-sided cooling is provided with a semiconductor chip between an upper board and a lower board of the power module. In particular, the upper board includes: a first bonding layer made of a dielectric material, and a first electrode made of a copper material and provided on a first surface of the first bonding layer, and the first electrode is connected to the semiconduc…
Who is the assignee on this patent?
Hyundai Motor Co Ltd, Kia Motors Corp
What technology area does this patent fall under?
Primary CPC classification H10W40/22. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 04 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 7 related publications on this page (citations in our corpus or others sharing the same primary CPC).