Power overlay structure and method of making same

Patent metadata

Field	Value
Publication number	US-10186477-B2
Application number	US-201615363237-A
Country	US
Kind code	B2
Filing date	Nov 29, 2016
Priority date	Mar 14, 2013
Publication date	Jan 22, 2019
Grant date	Jan 22, 2019

Abstract

A semiconductor device module includes a dielectric layer, a semiconductor device having a first surface coupled to the dielectric layer, and a conducting shim having a first surface coupled to the dielectric layer. The semiconductor device also includes an electrically conductive heatspreader having a first surface coupled to a second surface of the semiconductor device and a second surface of the conducting shim. A metallization layer is coupled to the first surface of the semiconductor device and the first surface of the conducting shim. The metallization layer extends through the dielectric layer and is electrically connected to the second surface of the semiconductor device by way of the conducting shim and the heatspreader.

First claim

What is claimed is:

1. A semiconductor package comprising:
a semiconductor device and a conducting shim coupled to a common surface of an insulating substrate;
a conductive slab stacked atop the semiconductor device and the conducting shim;
a conductive contact layer thermally and electrically coupling the conductive slab to the semiconductor device and the conducting shim, the conductive contact layer in direct physical contact with the conductive slab, the semiconductor device, and the conducting shim; and
a metallization layer extending through vias in the insulating substrate to electrically couple with the semiconductor device and the conducting shim.

2. The semiconductor package of claim 1 wherein the conductive contact layer comprises one of solder, sintered silver, and a conductive adhesive.

3. The semiconductor package of claim 1 wherein the metallization layer is electrically coupled to opposing surfaces of the semiconductor device.

4. The semiconductor package of claim 1 wherein the conductive slab and the conducting shim electrically couple the metallization layer to a surface of the semiconductor device positioned opposite the insulating substrate.

5. The semiconductor package of claim 1 wherein the conducting shim is sized such that a top surface thereof is substantially co-planar with a top surface of the semiconductor device.

6. The semiconductor package of claim 1 further comprising a thermal interface coating a top surface of the conductive slab.

7. The semiconductor package of claim 6 wherein the thermal interface comprises a multi-layer structure comprising an electrical insulator.

8. The semiconductor package of claim 6 further comprising a heat sink coupled to the conductive slab by way of the thermal interface.

9. A method of manufacturing a semiconductor package comprising:
providing an insulating substrate;
coupling a bottom surface of a semiconductor device to a first surface of the insulating substrate;
coupling a bottom surface of a conducting shim to the first surface of the insulating substrate;
applying a conductive contact layer directly to a top surface of the semiconductor device and a top surface of the conducting shim, wherein the conductive contact layer thermally and electrically couples a conductive slab to the semiconductor device and the conducting shim; and
forming a metallization layer on a second surface of the insulating substrate such that the metallization layer extends through vias in the insulating substrate to electrically couple with the semiconductor device and the conducting shim.

10. The method of claim 9 further comprising coupling the semiconductor device and the conducting shim to the insulating substrate with a layer of adhesive.

11. The method of claim 9 wherein applying the conductive contact layer comprises applying one of solder, sintered silver, and conductive adhesive.

12. The method of claim 9 further comprising applying a thermal interface across a top surface of the conductive slab.

13. The method of claim 12 further comprising coupling a heat sink to the conductive slab by way of the thermal interface.

14. The method of claim 9 further comprising sizing the conducting shim such that a top surface of the conducting shim and a top surface of the semiconductor device are substantially co-planar when the conducting shim and the semiconductor device are coupled to the insulating substrate.

15. A semiconductor package comprising:
an insulating substrate;
a semiconductor device having a bottom surface coupled to a first surface of the insulating substrate and a top surface opposite the bottom surface;
a conducting shim having a bottom surface coupled to the first surface of the insulating substrate and a top surface that is substantially co-planar with the top surface of the semiconductor device;
a heatspreader coupled to the top surface of the semiconductor device and the top surface of the conducting shim; and
a metallization layer formed on a second surface of the insulating substrate, the metallization layer extending through vias in the insulating substrate to electronically couple with the semiconductor device and the conducting shim.

16. The semiconductor package of claim 15 further comprising a conductive contact layer directly coupling the heatspreader to the semiconductor device and the conducting shim.

17. The semiconductor package of claim 16 wherein the conductive contact layer comprises one of solder, sintered silver, and conductive adhesive.

18. The semiconductor package of claim 15 wherein the metallization layer is electrically connected to the top surface of the semiconductor device through the conducting shim and the heatspreader.

19. The semiconductor package of claim 15 further comprising a heat sink coupled to the heatspreader by a thermal interface.

20. The semiconductor package of claim 19 wherein the thermal interface comprises a multi-layer structure with an electrical insulating layer therein.

Assignees

• Gen Electric

Inventors

• Gowda Arun Virupaksha
• Mcconnelee Paul Alan
• Chauhan Shakti Singh

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/093

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title