Leadless semiconductor packages, leadframes therefor, and methods of making

Patent metadata

Field	Value
Publication number	US-12424522-B2
Application number	US-202016984758-A
Country	US
Kind code	B2
Filing date	Aug 4, 2020
Priority date	Jan 29, 2009
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

A leadframe includes a frame, a die pad, a contact including a flank adjacent to the frame, a first tie bar between the frame and die pad, and a second tie bar between the die pad and contact. The leadframe is disposed over a carrier. A semiconductor die is disposed over the die pad. An encapsulant is deposited over the leadframe and semiconductor die including between the carrier and half-etched portions of the leadframe. A first trench is formed in the encapsulant to remove a portion of the frame and expose the flank of the contact. A conductive layer is formed over the flank by electroplating. A second trench is formed in the encapsulant through the second tie bar after forming the conductive layer.

First claim

What is claimed:

1. A semiconductor device, comprising:
a first semiconductor die, a second semiconductor die, a third semiconductor die, and a fourth semiconductor die;
a first plurality of contacts adjacent to the first semiconductor die, a second plurality of contacts adjacent to the second semiconductor die, a third plurality of contacts adjacent to the third semiconductor die, and a fourth plurality of contacts adjacent to the fourth semiconductor die;
a first plurality of tie bars adjacent to the first semiconductor die, a second plurality of tie bars adjacent to the second semiconductor die, a third plurality of tie bars adjacent to the third semiconductor die, and a fourth plurality of tie bars adjacent to the fourth semiconductor die;
an encapsulant coupled at least partially over each of the semiconductor die and each of the plurality of contacts; and
a first trench in a first surface of the encapsulant laterally adjacent to each of the plurality of contacts;
wherein a depth of the first trench extends across a full vertical thickness of at least two contacts within each of the plurality of contacts;
wherein, the first trench extends only partially into a thickness of the encapsulant;
wherein the first plurality of contacts and the second plurality of contacts are exposed on a first sidewall of the first trench and the third plurality of contacts and the fourth plurality of contacts are exposed on a second sidewall of the first trench; and
wherein the first plurality of contacts is opposite the fourth plurality of contacts and the second plurality of contacts is opposite the third plurality of contacts.

2. The device of claim 1 , further comprising a conductive layer over a flank of each contact of each of the plurality of contacts for the full vertical thickness of each of the contact of each plurality of contacts.

3. The device of claim 1 , further comprising a second trench in the first surface of the encapsulant between the first semiconductor die and the first plurality of contacts and between the second semiconductor die and the second plurality of contacts.

4. The device of claim 3 , wherein a depth of the second trench into the encapsulant is approximately equal to half of a thickness of the first plurality of contacts.

5. The device of claim 1 , further comprising a first die pad under the first semiconductor die, a second die pad under the second semiconductor die, a third die pad under the third semiconductor die, and a fourth die pad under the fourth semiconductor die.

6. The device of claim 1 , further comprising a bond wire extending from the first sidewall of the trench.

7. The device of claim 1 , wherein each of the plurality of tie bars is half-etched.

8. The device of claim 1 , further comprising a second trench between the first semiconductor die and the second semiconductor die and between the third semiconductor die and the fourth semiconductor die.

9. A semiconductor device, comprising:
a first semiconductor die, a second semiconductor die, a third semiconductor die, and a fourth semiconductor die;
a first plurality of contacts adjacent to the first semiconductor die, a second plurality of contacts adjacent to the second semiconductor die, a third plurality of contacts adjacent to the third semiconductor die, and a fourth plurality of contacts adjacent to the fourth semiconductor die;
a first plurality of tie bars adjacent to the first semiconductor die, a second plurality of tie bars adjacent to the second semiconductor die, a third plurality of tie bars adjacent to the third semiconductor die, and a fourth plurality of tie bars adjacent to the fourth semiconductor die;
an encapsulant coupled at least partially over each of the semiconductor die and each of the plurality of contacts;
a first plurality of trenches in a first surface of the encapsulant laterally adjacent to each of the plurality of contacts; and
a second plurality of trenches in the first surface of the encapsulant between the first semiconductor die and the first plurality of contacts, the second semiconductor die and the second plurality of contacts, the third semiconductor die and the third plurality of contacts, and the fourth semiconductor die and the fourth plurality of contacts wherein the first plurality of trenches extends across a full vertical thickness of each of the plurality of contacts to expose at least two contacts within each of the plurality of contacts.

10. The device of claim 9 , further comprising a conductive layer over a flank of each contact of each of the plurality of contacts for the full vertical thickness of each contact.

11. The device of claim 9 , wherein a depth of the second plurality of trenches into the encapsulant is approximately equal to half of a thickness of each of the plurality of contacts.

12. The device of claim 9 , wherein each of the plurality of tie bars is half-etched.

13. The device of claim 9 , wherein each of the semiconductor die is singulated through the first plurality of trenches.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Truhitte Darrell D
• Wang Soon Wei
• Chew Chee Hiong

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/755

  between a chip and a laterally-adjacent insulating package substrate, interpose or RDL · CPC title

• H10W76/17

  characterised by their materials · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title