Method of forming an electronic package and structure

Patent metadata

Field	Value
Publication number	US-9768091-B2
Application number	US-201213408058-A
Country	US
Kind code	B2
Filing date	Feb 29, 2012
Priority date	Feb 13, 2012
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

In one embodiment, an electronic package structure includes multiple rows of I/O pads and is formed without a flag portion. An electronic device may be attached to a pair of adjacent inner rows of I/O pads. The pair of adjacent inner rows of I/O pads is configured to support, at least in part, the electronic device, and to receive connective structures, such as wire bonds. Connective structures may electrically connect the electronic device to the multiple rows of I/O pads, and an encapsulating layer covers portions of the I/O pads, the electronic device and the connective structures.

First claim

I claim:

1. An electronic device structure comprising:
a leadframe having a pair of adjacent inner rows of I/O pads and at least one outer row of I/O pads, wherein the pair of adjacent inner rows of I/O pads are physically isolated from each other and each have an interior facing sidewall surface opposing each other;
an electronic device having first and second opposing major surfaces, wherein the second major surface is attached to at least two opposing I/O pads in the pair of adjacent inner rows of I/O pads;
connective structures coupling the first major surface to at least a portion of I/O pads in the pair of adjacent inner rows of I/O pads and the at least one outer row of I/O pads; and
an encapsulating layer covering at least portions of the leadframe, the electronic device and the connective structures, wherein the encapsulating layer is absent from a portion of the interior facing sidewall surface of each of the adjacent inner rows of I/O pads, wherein:
one I/O pad within the pair of adjacent inner rows of I/O pads is attached to the second major surface with a conductive material, and
a second I/O pad within the pair of adjacent inner rows of I/O pads is attached to the second major surface with a non-conductive material.

2. The structure of claim 1 , wherein the electronic device structure is configured as a quad-flat pack no-lead (QFN) package.

3. The structure of claim 1 , wherein the leadframe has at least two outer rows of I/O pads.

4. The structure of claim 1 , wherein the leadframe is absent a flag portion adjacent a central portion of the electronic device.

5. The structure of claim 1 further comprising a slot between the pair of adjacent inner rows of I/O pads underlying the electronic device.

6. The structure of claim 1 , wherein the second major surface is attached with a non-conductive adhesive.

7. The structure of claim 1 , wherein the connective structures comprise wire bonds.

Assignees

• Aripin Azhar
• Semiconductor Components Ind Llc

Inventors

• Aripin Azhar

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/681

  comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title